diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 20:48:08 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-07 21:30:02 +0000 |
| commit | 9c1c00968c943659bab2a817892e5a9be9dfb7c0 (patch) | |
| tree | 279fd6df2ad43db4bd6afb0e4c783f3596c00cad /src/mainboard/protectli/vault_kbl | |
| parent | c787a246f963621f1b48577881ac86fe5a3c15c7 (diff) | |
soc/intel/skylake: Enable thermal subsystem depending on devicetree
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/protectli/vault_kbl')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9071a7b377..16400111ac 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" @@ -219,6 +218,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI |