diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/protectli/vault_kbl/devicetree.cb | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/protectli/vault_kbl/devicetree.cb')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index f57f97832c..61481960e5 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -152,23 +152,6 @@ chip soc/intel/skylake # RP 9 shares CLKSRC5# with RP 6 register "PcieRpClkSrcNumber[8]" = "5" - - # USB 2.0 enable ports 1-8, disable ports 9-12 - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot - - # USB 3.0 enable ports 1-4, disable ports 5-6 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -185,7 +168,25 @@ chip soc/intel/skylake device domain 0 on device ref igpu on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [1] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [2] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [3] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [4] = USB2_PORT_SHORT(OC_SKIP), // Type-A Port + [5] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [6] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port + [7] = USB2_PORT_SHORT(OC_SKIP), // mPCIe slot + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [1] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [2] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + [3] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port + }" + end device ref heci1 on end device ref sata on end device ref pcie_rp1 on end |