diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-18 15:21:03 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-01-30 22:11:50 +0000 |
| commit | 486240fc7d2f1f8fc5bac2614d5f4139ab8d4ea3 (patch) | |
| tree | 23e4c847aa743f03125518e6cf103c072fe3cb28 /src/mainboard/protectli/vault_bsw | |
| parent | f58abca47a48c3f3e6cee2599b1fcb7619865169 (diff) | |
src/mainboard: Remove unnecessary space after casts
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw')
| -rw-r--r-- | src/mainboard/protectli/vault_bsw/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 33519b9d42..745cb82cb3 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -15,7 +15,7 @@ void mainboard_after_memory_init(void) * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32)0); ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); } |