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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-03-27 11:35:48 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-09 21:26:20 +0000
commit83565dea8638841e522b64e74a4240002bba789d (patch)
treee985b0f0ad961980be1bfb4e659939c6458c7d32 /src/mainboard/protectli/vault_bsw/devicetree.cb
parent9d422ef3816234195714abae43e3c2d31098e059 (diff)
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw/devicetree.cb')
-rw-r--r--src/mainboard/protectli/vault_bsw/devicetree.cb141
1 files changed, 141 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb
new file mode 100644
index 0000000000..94c083d13a
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/devicetree.cb
@@ -0,0 +1,141 @@
+chip soc/intel/braswell
+
+ ############################################################
+ # Set the parameters for MemoryInit
+ ############################################################
+
+ register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
+
+ register "PcdMrcInitMmioSize" = "0x0800"
+ register "PcdMrcInitSpdAddr1" = "0xa0"
+ register "PcdMrcInitSpdAddr2" = "0xa2"
+ register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
+ register "PcdApertureSize" = "2"
+ register "PcdGttSize" = "1"
+ register "PcdDvfsEnable" = "0"
+ register "PcdCaMirrorEn" = "1"
+
+ ############################################################
+ # Set the parameters for SiliconInit
+ ############################################################
+
+ register "PcdSdcardMode" = "PCH_DISABLED"
+ register "PcdEnableHsuart0" = "0"
+ register "PcdEnableHsuart1" = "0"
+ register "PcdEnableAzalia" = "1"
+ register "PcdEnableXhci" = "1"
+ register "PcdEnableLpe" = "0"
+ register "PcdEnableDma0" = "0"
+ register "PcdEnableDma1" = "0"
+ register "PcdEnableI2C0" = "0"
+ register "PcdEnableI2C1" = "0"
+ register "PcdEnableI2C2" = "0"
+ register "PcdEnableI2C3" = "0"
+ register "PcdEnableI2C4" = "0"
+ register "PcdEnableI2C5" = "0"
+ register "PcdEnableI2C6" = "0"
+ register "PunitPwrConfigDisable" = "1" # Disable SVID
+ register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
+ register "PcdEmmcMode" = "PCH_DISABLED"
+ register "PcdUsb3ClkSsc" = "1"
+ register "PcdDispClkSsc" = "1"
+ register "PcdSataClkSsc" = "1"
+ register "PcdEnableSata" = "1"
+ register "Usb2Port0PerPortPeTxiSet" = "7"
+ register "Usb2Port0PerPortTxiSet" = "6"
+ register "Usb2Port0IUsbTxEmphasisEn" = "3"
+ register "Usb2Port0PerPortTxPeHalf" = "1"
+ register "Usb2Port1PerPortPeTxiSet" = "7"
+ register "Usb2Port1PerPortTxiSet" = "6"
+ register "Usb2Port1IUsbTxEmphasisEn" = "3"
+ register "Usb2Port1PerPortTxPeHalf" = "1"
+ register "Usb2Port2PerPortPeTxiSet" = "7"
+ register "Usb2Port2PerPortTxiSet" = "6"
+ register "Usb2Port2IUsbTxEmphasisEn" = "3"
+ register "Usb2Port2PerPortTxPeHalf" = "1"
+ register "Usb2Port3PerPortPeTxiSet" = "7"
+ register "Usb2Port3PerPortTxiSet" = "6"
+ register "Usb2Port3IUsbTxEmphasisEn" = "3"
+ register "Usb2Port3PerPortTxPeHalf" = "1"
+ register "Usb2Port4PerPortPeTxiSet" = "7"
+ register "Usb2Port4PerPortTxiSet" = "6"
+ register "Usb2Port4IUsbTxEmphasisEn" = "3"
+ register "Usb2Port4PerPortTxPeHalf" = "1"
+ register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+ register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+ register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+ register "PcdSataInterfaceSpeed" = "3"
+ register "PcdPchSsicEnable" = "1"
+ register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
+ register "PMIC_I2CBus" = "0"
+ register "ISPEnable" = "0" # Disable IUNIT
+ register "ISPPciDevConfig" = "3"
+ register "PcdSdDetectChk" = "0" # Disable SD card detect
+ register "DptfDisable" = "1"
+
+ # Enable devices in PCI mode
+ register "lpss_acpi_mode" = "0"
+ register "emmc_acpi_mode" = "0"
+ register "sd_acpi_mode" = "0"
+ register "lpe_acpi_mode" = "0"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ # Enable SERIRQ continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # 8086 2280 - SoC transaction router
+ device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX
+ device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
+ device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF
+ device pci 10.0 off end # 8086 2294 - MMC Port
+ device pci 12.0 off end # 8086 2296 - SD Port
+ device pci 13.0 on end # 8086 22a3 - Sata controller
+ device pci 14.0 on end # 8086 22b5 - USB XHCI
+ device pci 18.0 off end # 8086 22c0 - SIO - DMA
+ device pci 18.1 off end # 8086 22c1 - I2C Port 1
+ device pci 18.2 off end # 8086 22c2 - I2C Port 2
+ device pci 18.3 off end # 8086 22c3 - I2C Port 3
+ device pci 18.4 off end # 8086 22c4 - I2C Port 4
+ device pci 18.5 off end # 8086 22c5 - I2C Port 5
+ device pci 18.6 off end # 8086 22c6 - I2C Port 6
+ device pci 18.7 off end # 8086 22c7 - I2C Port 7
+ device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine
+ device pci 1b.0 on end # 8086 2284 - HD Audio
+ device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1
+ device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2
+ device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3
+ device pci 1c.3 on # 8086 22ce - PCIe Root Port 4
+ smbios_slot_desc
+ "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "WIFI" "SlotDataBusWidth1X"
+ end
+ device pci 1e.0 off end # 8086 2286 - SIO - DMA
+ device pci 1e.3 off end # 8086 228a - HSUART 1
+ device pci 1e.4 off end # 8086 228c - HSUART 2
+ device pci 1f.0 on # 8086 229c - LPC bridge
+ chip superio/ite/it8613e
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # Environment Controller
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.3 on end # 8086 2292 - SMBus 0
+ end
+end