diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-03-27 11:35:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:26:20 +0000 |
| commit | 83565dea8638841e522b64e74a4240002bba789d (patch) | |
| tree | e985b0f0ad961980be1bfb4e659939c6458c7d32 /src/mainboard/protectli/vault_bsw/Kconfig | |
| parent | 9d422ef3816234195714abae43e3c2d31098e059 (diff) | |
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw/Kconfig')
| -rw-r--r-- | src/mainboard/protectli/vault_bsw/Kconfig | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_bsw/Kconfig b/src/mainboard/protectli/vault_bsw/Kconfig new file mode 100644 index 0000000000..499bad4f99 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/Kconfig @@ -0,0 +1,78 @@ +if BOARD_PROTECTLI_FW2B || BOARD_PROTECTLI_FW4B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CACHE_MRC_SETTINGS + select DISABLE_HPET + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select PCIEXP_L1_SUB_STATE + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select SOC_INTEL_BRASWELL + select SPI_FLASH_MACRONIX + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + string + default protectli/vault_bsw + +config VARIANT_DIR + string + default "fw2b" if BOARD_PROTECTLI_FW2B + default "fw4b" if BOARD_PROTECTLI_FW4B + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "FW2B" if BOARD_PROTECTLI_FW2B + default "FW4B" if BOARD_PROTECTLI_FW4B + +config MAINBOARD_VENDOR + string + default "Protectli" + +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 256 + +config MAX_CPUS + int + default 2 if BOARD_PROTECTLI_FW2B + default 4 if BOARD_PROTECTLI_FW4B + +config CBFS_SIZE + hex + default 0x500000 + +config PXE_ROM_ID + string + default "8086,1539" if BOARD_PROTECTLI_FW2B + default "8086,157b" if BOARD_PROTECTLI_FW4B + +if !RUN_FSP_GOP +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/protectli/vault_bsw/vgabios.bin" + help + The C0 version of the video bios gets computed from this name + so that they can both be added. Only the correct one for the + system will be run. + +config VGA_BIOS_ID + string + default "8086,22b0" + help + The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + in soc/intel/braswell/Makefile.inc as 8086,22b1 + +endif #RUN_FSP_GOP + +endif # BOARD_PROTECTLI_FW2B |