soc/amd/mendocino: Add VRM limit DPTC registers

Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.

b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions