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authorLean Sheng Tan <sheng.tan@9elements.com>2022-06-02 18:34:44 +0200
committerMartin L Roth <gaumless@tutanota.com>2022-06-05 19:57:00 +0000
commitde498a2fff08e9572f58dea72791a68de5ad16d4 (patch)
tree42d247fbc64da7de8b60c0a72fd464d70619f74c /src/mainboard/prodrive
parente4998d1cd232f89c42f880d0b394613d67426c15 (diff)
mb/prodrive/atlas: Update pcie config for i225
Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/prodrive')
-rw-r--r--src/mainboard/prodrive/atlas/devicetree.cb7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index 3b88508e39..3d75f5d7bd 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -55,7 +55,7 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
- # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80)
+ # Enable PCH PCIE RP 5, 6, 7, 8, 9 using free running CLK (0x80)
# Clock source is shared hence marked as free running.
register "pch_pcie_rp[PCH_RP(5)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED,
@@ -72,12 +72,13 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(9)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED,
}"
+ # Enable PCIe-to-i225 bridge using clk 1
register "pch_pcie_rp[PCH_RP(10)]" = "{
- .flags = PCIE_RP_CLK_SRC_UNUSED,
+ .clk_src = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_DISABLE,
}"
register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
- register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
# Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
# Clock source is shared hence marked as free running.