From de498a2fff08e9572f58dea72791a68de5ad16d4 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Thu, 2 Jun 2022 18:34:44 +0200 Subject: mb/prodrive/atlas: Update pcie config for i225 Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/mainboard/prodrive/atlas/devicetree.cb | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mainboard/prodrive') diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 3b88508e39..3d75f5d7bd 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -55,7 +55,7 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80) + # Enable PCH PCIE RP 5, 6, 7, 8, 9 using free running CLK (0x80) # Clock source is shared hence marked as free running. register "pch_pcie_rp[PCH_RP(5)]" = "{ .flags = PCIE_RP_CLK_SRC_UNUSED, @@ -72,12 +72,13 @@ chip soc/intel/alderlake register "pch_pcie_rp[PCH_RP(9)]" = "{ .flags = PCIE_RP_CLK_SRC_UNUSED, }" + # Enable PCIe-to-i225 bridge using clk 1 register "pch_pcie_rp[PCH_RP(10)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_DISABLE, }" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" - register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) # Clock source is shared hence marked as free running. -- cgit v1.2.3