mb, soc/intel: Reorganize CNVi device entries in devicetree

This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.

Before:
chip drivers/wifi/generic
	register "wake" = "..."
	device pci xx.y on end
end

After:
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "..."
		device generic 0 on end
	end
end

Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

1 files changed, 6 insertions, 4 deletions

diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 04e6774f65..2c0c26a92f 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -164,10 +164,12 @@ chip soc/intel/cannonlake
 		device pci 02.0 on      # Integrated Graphics Device
 			register "InternalGfx" = "1"
 		end
-		chip drivers/wifi/generic
-			register "wake" = "PME_B0_EN_BIT"
-			device pci 14.3 on  end # CNVi wifi
-		end
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "PME_B0_EN_BIT"
+				device generic 0 on end
+			end
+		end  # CNVi wifi
 
 		# This device does not have any function on CNP-H, but it needs
 		# to be here so that the resource allocator is aware of UART 2.