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| author | Harsha B R <harsha.b.r@intel.com> | 2022-12-16 12:30:28 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-12-29 07:10:46 +0000 |
| commit | ec0a85b5807320695a89cba6bffcaca6d0bbc0f1 (patch) | |
| tree | e65f5bd9afc3e4cb70bce5868bb2ee4c428d37b2 /src/mainboard/portwell | |
| parent | 2bd18edc84b4d9be3a251880d4921f58b0f11d5f (diff) | |
mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVP
Configure GPIO Tier-1 GPE's that defines the route for GPE
events for MTL-RVP. Configure GPE route as below,
PMC_GPE0_DW0 -> GPP_B
PMC_GPE0_DW1 -> GPP_D
PMC_GPE0_DW2 -> GPP_E
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to ChromeOS
using subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/portwell')
0 files changed, 0 insertions, 0 deletions