diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-01 23:22:55 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:57:06 +0000 |
| commit | f9decbb0c720662d8e71fe221aef55b7ecf76196 (patch) | |
| tree | 06b2198767b4c86b7d36e7ddd6a5f56b4a1fbc54 /src/mainboard/pcengines | |
| parent | e56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d (diff) | |
mb/*/*: Remove AMD family14 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines')
30 files changed, 0 insertions, 2678 deletions
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c deleted file mode 100644 index aff72ca0cd..0000000000 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <AGESA.h> -#include <spd_bin.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <SB800.h> - -#include "gpio_ftns.h" - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; - return AGESA_SUCCESS; -} - -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_RAMINIT) - return AGESA_UNSUPPORTED; - - u8 index = get_spd_offset(); - - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) - die("No SPD data\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig deleted file mode 100644 index 46f4ddec59..0000000000 --- a/src/mainboard/pcengines/apu1/Kconfig +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_PCENGINES_APU1 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_NUVOTON_NCT5104D - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_2048 - select HAVE_SPD_IN_CBFS - select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS - select MEMORY_MAPPED_TPM - -config MAINBOARD_DIR - default "pcengines/apu1" - -config MAINBOARD_PART_NUMBER - default "apu1" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9802" - -config SB800_AHCI_ROM - bool - default n - -choice - prompt "J19 pins 1-10" - default APU1_PINMUX_OFF_C - -config APU1_PINMUX_OFF_C - bool "disable" - -config APU1_PINMUX_GPIO0 - bool "GPIO" - -config APU1_PINMUX_UART_C - bool "UART 0x3e8" - -endchoice - -config UART_C_RS485 - bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C - -choice - prompt "J19 pins 11-20" - default APU1_PINMUX_OFF_D - -config APU1_PINMUX_OFF_D - bool "disable" - -config APU1_PINMUX_GPIO1 - bool "GPIO" - -config APU1_PINMUX_UART_D - bool "UART 0x2e8" - -endchoice - -config UART_D_RS485 - bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D - -config DIMM_SPD_SIZE - default 128 - -endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/Kconfig.name b/src/mainboard/pcengines/apu1/Kconfig.name deleted file mode 100644 index 265f7a6bde..0000000000 --- a/src/mainboard/pcengines/apu1/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_PCENGINES_APU1 - bool "APU1" diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc deleted file mode 100644 index bec5873b02..0000000000 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c -romstage-y += gpio_ftns.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c -ramstage-y += gpio_ftns.c - - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = HYNIX-H5TQ2G83CFR -SPD_SOURCES += HYNIX-H5TQ4G83MFR diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c deleted file mode 100644 index 254947cf8c..0000000000 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <PlatformMemoryConfiguration.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 4) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 7) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = NULL, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM), - - // APU soldered down memory uses memory CLK0 and CLK1 on CS0 - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - // APU soldered down memory requires different seeds -#define WLSEED 0x08 -#define RXSEED 0x40 - WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; - /* Bank interleaving is not supported on this platform */ - InitPost->MemConfig.EnableBankIntlv = FALSE; -} diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h deleted file mode 100644 index fdd5de0cd1..0000000000 --- a/src/mainboard/pcengines/apu1/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - - -#endif diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl deleted file mode 100644 index aa235f9f79..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/buttons.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (BTNS) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionInputOnly, - "\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {187} - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-keys-polled"}}, - Package () {"poll-interval", 100}, - Package () {"autorepeat", 1} - } - }) - - Device (BTN1) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* BTN_1 is 0x101 in linux/input.h */ - Package () {"linux,code", 257}, - Package () {"linux,input-type", 1}, - /* labeled S1 on the board, MODESW in the gpio header files */ - Package () {"label", "switch1"}, - Package () {"gpios", Package () {^^BTNS, 0, 0, 1 /* low-active */}}, - } - }) - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl deleted file mode 100644 index 705abf17f6..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu1/acpi/gpio.asl b/src/mainboard/pcengines/apu1/acpi/gpio.asl deleted file mode 100644 index 20bbf60a56..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/gpio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (GPIO) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - /* ACPI_MMIO_BASE + gpio offset */ - Memory32Fixed(ReadWrite, 0xFED80100, 0x0000100) - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-sb8xx"}}, - } - }) - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl deleted file mode 100644 index 128e0f1f24..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/leds.asl +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (LEDS) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {189, 190, 191} - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-leds"}}, - } - }) - - Device (LED1) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* - * From Linux Documentation/leds/leds-class.txt: - * LED Device Naming - * Is currently of the form: - * "devicename:colour:function" - */ - Package () {"label", "apu1:green:led1"}, - Package () {"gpios", Package () {^^LEDS, 0, 0, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } }) } - - Device (LED2) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"label", "apu1:green:led2"}, - Package () {"gpios", Package () {^^LEDS, 0, 1, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } - }) - } - - Device (LED3) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"label", "apu1:green:led3"}, - Package () {"gpios", Package () {^^LEDS, 0, 2, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } - }) - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl deleted file mode 100644 index deef1ec22c..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ /dev/null @@ -1,315 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ - Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: PCIe */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl deleted file mode 100644 index 6d9ff03005..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (P0IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (P1IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (P2IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (P3IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (\_SB.P0IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P0PR = 1 - } - - if (\_SB.P1PR) { - if (\_SB.P1IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P1PR = 1 - } - - if (\_SB.P2PR) { - if (\_SB.P2IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P2PR = 1 - } - - if (\_SB.P3PR) { - if (\_SB.P3IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P3PR = 1 - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl deleted file mode 100644 index 3b6fd02055..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (Arg0 == 3){ - URRE = 0 - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - HPDE = 1 - - /* Restore PCIRST# so it resets USB */ - if (Arg0 == 3){ - URRE = 1 - } - - /* Arbitrarily clear PciExpWakeStatus */ - Local1 = PWST - PWST = Local1 - - /* if (DeRefOf(WKST [0])) { - * WKST [1] = 0 - * } else { - * WKST [1] = Arg0 - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/pcengines/apu1/acpi/superio.asl b/src/mainboard/pcengines/apu1/acpi/superio.asl deleted file mode 100644 index d2d8a44c23..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl deleted file mode 100644 index e4ed275617..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - CMTI = 0x13 - GPSL = 0 -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If (UOM0 <= 9) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if (GPB0 == PLC0) { - PLC0 = ~PLC0 - \_SB.PT0D = PLC0 - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (UOM1 <= 9) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (GPB1 == PLC1) { - PLC1 = ~PLC1 - \_SB.PT1D = PLC1 - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (UOM2 <= 9) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (GPB2 == PLC2) { - PLC2 = ~PLC2 - \_SB.PT2D = PLC2 - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (UOM3 <= 9) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (GPB3 == PLC3) { - PLC3 = ~PLC3 - \_SB.PT3D = PLC3 - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (UOM4 <= 9) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (GPB4 == PLC4) { - PLC4 = ~PLC4 - \_SB.PT4D = PLC4 - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (UOM5 <= 9) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (GPB5 == PLC5) { - PLC5 = ~PLC5 - \_SB.PT5D = PLC5 - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (UOM6 <= 9) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (GPB6 == PLC6) { - PLC6 = ~PLC6 - \_SB.PT6D = PLC6 - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (UOM7 <= 9) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (GPB7 == PLC7) { - PLC7 = ~PLC7 - \_SB.PT7D = PLC7 - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (UOM8 <= 9) { - Scope (\_GPE) { - Method (_L17) { - if (G8IS == PLC8) { - PLC8 = ~PLC8 - \_SB.PT8D = PLC8 - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (UOM9 <= 9) { - Scope (\_GPE) { - Method (_L0E) { - if (G9IS == 0) { - \_SB.PT9D = 1 - } - } - } -} diff --git a/src/mainboard/pcengines/apu1/board_info.txt b/src/mainboard/pcengines/apu1/board_info.txt deleted file mode 100644 index 68d347d93a..0000000000 --- a/src/mainboard/pcengines/apu1/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Board name: apu1 -Board URL: http://www.pcengines.ch/apu1d4.htm -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c deleted file mode 100644 index 2016e7b6fa..0000000000 --- a/src/mainboard/pcengines/apu1/bootblock.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_type.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> - -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - -void bootblock_mainboard_early_init(void) -{ - if (CONFIG_UART_FOR_CONSOLE == 1) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c deleted file mode 100644 index 255893833c..0000000000 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Select the CPU family */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE - -/* Agesa optional capabilities selection */ -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_ENABLE_DMI TRUE - -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE - -/* Agesa configuration values selection */ -#include <AGESA.h> - -/* Include the files that instantiate the configuration definitions */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/* Instantiate all solution relevant data */ -#include <PlatformInstall.h> diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default deleted file mode 100644 index 06b04332a2..0000000000 --- a/src/mainboard/pcengines/apu1/cmos.default +++ /dev/null @@ -1,2 +0,0 @@ -boot_option=Fallback -debug_level=Debug diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout deleted file mode 100644 index e36dd6bd61..0000000000 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ /dev/null @@ -1,31 +0,0 @@ -entries - -# <start-bit> <bit-length> <config> <config-id> <parameter-name> -0 384 r 0 reserved_memory -384 4 r 0 reboot_bits -# leave 3 bits to make checksummed area start byte-aligned -392 1 e 2 boot_option -400 4 e 4 debug_level -# leave 7 bits to make checksummed area end byte-aligned -408 16 h 0 check_sum - -enumerations - -#<config-id> <value> <label> -## for boot_option -2 0 Fallback -2 1 Normal -## for debug_level -4 0 Emerg -4 1 Alert -4 2 Crit -4 3 Err -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew - -checksums - -checksum 392 407 408 diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb deleted file mode 100644 index f8efc24242..0000000000 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ /dev/null @@ -1,94 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 - device pci 0.0 on end # Root Complex - device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 - device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 - device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on end # SMBus - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - register "irq_trigger_type" = "0" - register "reset_gpios" = "1" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 off - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 off - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.008 off end - device pnp 2e.108 on - io 0x60 = 0x220 - end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 off end - device pnp 2e.107 off end - device pnp 2e.607 off end - device pnp 2e.f on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end # LPC TPM - end #LPC - device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 - device pci 14.5 off end # OHCI FS/LS USB - #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - register "disconnect_pcib" = "1" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - - chip northbridge/amd/agesa/family14 - # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end # agesa northbridge - - end #domain -end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl deleted file mode 100644 index f74bc59f45..0000000000 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" - #include "acpi/usb_oc.asl" - - /* Contains the GPIO led and button setup for this board */ - #include "acpi/buttons.asl" - #include "acpi/gpio.asl" - #include "acpi/leds.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c deleted file mode 100644 index 2c2eb9f7bd..0000000000 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <amdblocks/acpimmio_legacy_gpio100.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include "gpio_ftns.h" - -void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting) -{ - u8 bdata; - - iomux_write8(gpio, iomux_ftn); - - bdata = gpio_100_read8(gpio); - bdata &= 0x07; - bdata |= setting; /* set direction and data value */ - gpio_100_write8(gpio, bdata); -} - -u8 read_gpio(u8 gpio) -{ - return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0; -} - -int get_spd_offset(void) -{ - u8 spd_offset = read_gpio(GPIO_16); - return spd_offset; -} diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h deleted file mode 100644 index 79ed4a6d77..0000000000 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef GPIO_FTNS_H -#define GPIO_FTNS_H - -#include <stdint.h> - -void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting); -u8 read_gpio(u8 gpio); -int get_spd_offset(void); - -#define GPIO_10 10 // PE3 Reset -#define GPIO_11 11 // PE4 Reset -#define GPIO_15 15 // board rev strap ms bit -#define GPIO_16 16 // board rev strap ls bit -#define GPIO_17 17 // TP13 -#define GPIO_18 18 // TP10 -#define GPIO_187 187 // MODESW -#define GPIO_189 189 // LED1# -#define GPIO_190 190 // LED2# -#define GPIO_191 191 // LED3# -#define GPIO_FTN_1 0x01 -#define GPIO_OUTPUT 0x08 -#define GPIO_INPUT 0x28 -#define GPIO_DATA_IN 0x80 -#define GPIO_DATA_LOW 0x00 -#define GPIO_DATA_HIGH 0x40 - -#endif /* GPIO_FTNS_H */ diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c deleted file mode 100644 index 06880eb107..0000000000 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c deleted file mode 100644 index f7b34f0c3c..0000000000 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> - -#include <console/console.h> -#include <device/device.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <southbridge/amd/common/amd_pci_util.h> -#include <smbios.h> -#include <string.h> -#include <southbridge/amd/cimx/sb800/pci_devs.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <northbridge/amd/agesa/family14/pci_devs.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include "gpio_ftns.h" -#include <AGESA.h> -#include <AMD.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. - * - * The PCI INTA/B/C/D pins are connected to - * FCH pins INTE/F/G/H on the schematic so these need - * to be routed as well. - */ -static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ - [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, - /* IDE, SATA */ - [0x40] = 0x0B,0x0B, - /* GPPInt0 - 3 */ - [0x50] = 0x0A,0x0B,0x0A,0x0B -}; - -static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - /* INTA# - INTH# */ - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, - /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, - /* IMC INT0 - 5 */ - [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19/22/20 INTA-C */ - [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, - /* IDE, SATA */ - [0x40] = 0x11,0x13, - /* GPPInt0 - 3 */ - [0x50] = 0x10,0x11,0x12,0x13 -}; - -/* - * This table defines the index into the picr/intr_data - * tables for each device. Any enabled device and slot - * that uses hardware interrupts should have an entry - * in this table to define its index into the FCH - * PCI_INTR register 0xC00/0xC01. This index will define - * the interrupt that it should use. Putting PIRQ_A into - * the PIN A index for a device will tell that device to - * use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -/* - * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because of PCI INT_PIN swizzle isn't implemented to match - * the IDSEL (dev 3) of the slot, the table is adjusted for the - * swizzle and INTA is connected to PIRQH so PINA/B/C/D on - * off-chip devices should get mapped to PIRQH/E/F/G. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ - {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 05.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 06.0 */ - {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 07.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ - {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ - {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 15.0 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit - * once configuration file format for SPI flash storage is complete. - */ -#define SIO_PORT 0x2e - -static void config_gpio_mux(void) -{ - struct device *uart, *gpio; - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); - if (uart) - uart->enabled = CONFIG(APU1_PINMUX_UART_C); - if (gpio) - gpio->enabled = CONFIG(APU1_PINMUX_GPIO0); - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); - if (uart) - uart->enabled = CONFIG(APU1_PINMUX_UART_D); - if (gpio) - gpio->enabled = CONFIG(APU1_PINMUX_GPIO1); -} - -static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) -{ - struct resource *res; - res = new_resource(dev, reg); - res->base = val; - res->size = 0; - res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; -} - -static void config_addon_uart(void) -{ - struct device *uart; - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - if (uart && uart->enabled && CONFIG(UART_C_RS485)) - pnp_raw_resource(uart, 0xf2, 0x12); - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - if (uart && uart->enabled && CONFIG(UART_D_RS485)) - pnp_raw_resource(uart, 0xf2, 0x12); -} - -/********************************************** - * Enable the dedicated functions of the board. - **********************************************/ -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, unsigned long *current) -{ - const u32 max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */ - - struct smbios_type16 *t = smbios_carve_table(*current, SMBIOS_PHYS_MEMORY_ARRAY, - sizeof(*t), *handle); - - t->use = MEMORY_ARRAY_USE_SYSTEM; - t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; - t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection; - t->maximum_capacity = max_capacity * 1024 * 1024; - t->memory_error_information_handle = 0xfffe; - t->number_of_memory_devices = 1; - - const int len = smbios_full_table_len(&t->header, t->eos); - *current += len; - return len; -} - -static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, unsigned long *current) -{ - struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE, - sizeof(*t), *handle + 1); - - t->phys_memory_array_handle = *handle; - t->memory_error_information_handle = 0xfffe; - t->total_width = agesa_dmi->T17[0][0][0].TotalWidth; - t->data_width = agesa_dmi->T17[0][0][0].DataWidth; - t->size = agesa_dmi->T17[0][0][0].MemorySize; - /* AGESA DMI returns form factor = 0, override it with SPD value */ - t->form_factor = MEMORY_FORMFACTOR_SODIMM; - t->device_set = agesa_dmi->T17[0][0][0].DeviceSet; - t->device_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].DeviceLocator); - t->bank_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].BankLocator); - t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; - t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; - t->speed = agesa_dmi->T17[0][0][0].Speed; - t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; - t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber); - t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber); - t->attributes = agesa_dmi->T17[0][0][0].Attributes; - t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; - t->minimum_voltage = 1500; /* From SPD: 1.5V */ - t->maximum_voltage = 1500; - - const int len = smbios_full_table_len(&t->header, t->eos); - *current += len; - return len; -} - -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - DMI_INFO *agesa_dmi; - int len; - - agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); - - if (!agesa_dmi) - return 0; - - len = mainboard_smbios_type16(agesa_dmi, handle, current); - len += mainboard_smbios_type17(agesa_dmi, handle, current); - - *handle += 2; - - return len; -} -#endif - -static void mainboard_enable(struct device *dev) -{ - /* Maintain this text unchanged for manufacture process. */ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - config_gpio_mux(); - config_addon_uart(); - - /* Power off unused clock pins of GPP PCIe devices - * GPP CLK0-2 are connected to the 3 ethernet chips - * GPP CLK3-4 are connected to the miniPCIe slots - */ - misc_write8(0, 0x21); - misc_write8(1, 0x43); - /* GPP CLK5 is only connected to test pads -> disable */ - misc_write8(2, 0x05); - /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ - misc_write8(3, 0); - misc_write8(4, 0); - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif -} - -/* - * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address - * into the smbios serial number location. - */ -const char *smbios_mainboard_serial_number(void) -{ - static char serial[10]; - struct device *dev; - uintptr_t bar18; - u32 mac_addr = 0; - int i; - - /* Already initialized. */ - if (serial[0] != 0) - return serial; - - dev = pcidev_on_root(4, 0); - if (dev) - dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); - if (!dev) - return serial; - - /* Read in the last 3 bytes of NIC's MAC address. */ - bar18 = pci_read_config32(dev, PCI_BASE_ADDRESS_2); - bar18 &= 0xFFFFFFF0; - for (i = 3; i < 6; i++) { - mac_addr <<= 8; - mac_addr |= read8((u8 *)bar18 + i); - } - mac_addr &= 0x00FFFFFF; - mac_addr /= 4; - mac_addr -= 64; - - snprintf(serial, sizeof(serial), "%d", mac_addr); - return serial; -} - -/* - * Set up "Over Current Control 1" (reg 0x58) on the first OHCI device. - * The remaining ports on the second device are for mcpie2/sdcard and - * can stay at the power-on default value. - * - * The schematic shows this transposed mapping for the first device: - * chipset port 0 -> port 1 (j12 external 2, usboc0#) - * chipset port 1 -> port 4 (j17 mpcie1) - * chipset port 2 -> port 2 (j14 header row1, usboc1#) - * chipset port 3 -> port 3 (j14 header row2, usboc1#) - * chipset port 4 -> port 0 (j12 external 1. usboc0#) - * - * Register mapping: - * bit0-3: Mapping for HS Port 0 - * bit4-7: Mapping for HS Port 1 - * bit8-11: Mapping for HS Port 2 - * bit12-15: Mapping for HS Port 3 - * bit16-19: Mapping for HS Port 4 - * bit20-31: Reserved (0) - * - * power-on default: 0xfffff - * A value >7 will disable the overcurrent detection. - */ -static void usb_oc_setup(void) -{ - struct device *dev = pcidev_on_root(0x12, 0); - - pci_write_config32(dev, 0x58, 0x011f0); -} - -/* - * We will stuff the memory size into the smbios sku location. - */ -const char *smbios_system_sku(void) -{ - static char sku[5]; - if (sku[0] != 0) - return sku; - - if (!get_spd_offset()) - snprintf(sku, sizeof(sku), "2 GB"); - else - snprintf(sku, sizeof(sku), "4 GB"); - return sku; -} - -static void mainboard_final(void *chip_info) -{ - /* Maintain this text unchanged for manufacture process. */ - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); - - /* - * LED1/D7/GPIO_189 should be 0 - * LED2/D6/GPIO_190 should be 1 - * LED3/D5/GPIO_191 should be 1 - */ - configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - usb_oc_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h deleted file mode 100644 index 44172f67d6..0000000000 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/* APU has no legacy P/S2 controller */ -#define LEGACY_FREE 0 /* setting legacy free disables I/O access to 0x3F8 */ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 - */ -#define USB_CONFIG 0x7F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 -> connected to LPC devices - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x02 - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is defined at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is defined at BIT2 & BIT3 - * SDIN2 is defined at BIT4 & BIT5 - * SDIN3 is defined at BIT6 & BIT7 - */ -//#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 0 - -/** - * @def USB_RX_MODE - * 0x00 - leave Cg2Pll voltage at default value (1.222V) - * 0x01 - lower Cg2Pll voltage to 1.1V - * - * Workaround for reset issues via outb(0x6, 0xcf9). - * For details check: - * AMD SB800 Family Product Errata, - * Section 15. USB Resets Asynchronously With Port CF9h Hard Reset - * - */ - -#define USB_RX_MODE 0x00 - -#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c deleted file mode 100644 index f5948274fb..0000000000 --- a/src/mainboard/pcengines/apu1/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <northbridge/amd/agesa/state_machine.h> -#include "gpio_ftns.h" -#include <SB800.h> -#include <sb_cimx.h> - -static void early_lpc_init(void) -{ - /* PC Engines requires system boot when power is applied. This feature is - * controlled in PM_REG 5Bh register. "Always Power On" works by writing a - * value of 05h. - */ - u8 bdata = pm_read8(SB_PMIOA_REG5B); - bdata &= 0xf8; //clear bits 0-2 - bdata |= 0x05; //set bits 0,2 - pm_write8(SB_PMIOA_REG5B, bdata); - - /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ - bdata = pm_read8(SB_PMIOA_REGEA); - bdata &= 0xfe; //clear bit 0 - bdata |= 0x01; //set bit 0 - pm_write8(SB_PMIOA_REGEA, bdata); - - //configure required GPIOs - configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - early_lpc_init(); -} diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex deleted file mode 100644 index 72377c4257..0000000000 --- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex +++ /dev/null @@ -1,234 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# HYNIX-H5TQ2G83CFR - -# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -03 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[7:6]: reserved -19 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 1 = 8 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -01 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1 / 1 = 1.0 ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0c = tCKmin of 1.5 ns = in multiples of MTB -0C - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -7E 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.5ns - DDR3-1333 -6C - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x30 = 6ns -30 - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x120 = 36ns - DDR3-1333 (see byte 21) -20 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x28C = 49.5ns - DDR3-1333 -8C - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -00 05 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x00F0 = 30ns - DDR3-1333, 1 KB page size -00 F0 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 2 = Signal Loading -# bits[3:2]: reserved -# bits[6:4]: 4 = Die count -# bit7 : 0 = Standard Monolithic DRAM Device -42 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 (reserved) -00 - -# 40 - 47 (reserved) -00 00 00 00 00 00 00 00 - -# 48 - 55 (reserved) -00 00 00 00 00 00 00 00 - -# 56 - 59 (reserved) -00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 71 (reserved) -00 00 00 00 00 00 00 00 - -# 72 - 79 (reserved) -00 00 00 00 00 00 00 00 - -# 80 - 87 (reserved) -00 00 00 00 00 00 00 00 - -# 88 - 95 (reserved) -00 00 00 00 00 00 00 00 - -# 96 - 103 (reserved) -00 00 00 00 00 00 00 00 - -# 104 - 111 (reserved) -00 00 00 00 00 00 00 00 - -# 112 - 116 (reserved) -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -00 - -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -13 12 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -c4 1b diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex deleted file mode 100644 index b6d24b48a1..0000000000 --- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex +++ /dev/null @@ -1,237 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# HYNIX-H5TQ4G83MFR - -# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -04 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[5:3]: 4 = 16 Row Address Bits -# bits[7:6]: reserved -21 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 1 = 8 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -01 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1 / 1 = 1.0 ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0c = tCKmin of 1.5 ns = in multiples of MTB -0C - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -7E 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.5ns - DDR3-1333 -6C - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x30 = 6ns -30 - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x120 = 36ns - DDR3-1333 (see byte 21) -20 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x28C = 49.5ns - DDR3-1333 -8C - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -# 0x820 = 260ns - for 4 Gigabit chips -20 08 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x00F0 = 30ns - DDR3-1333, 1 KB page size -00 F0 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 2 = Signal Loading -# bits[3:2]: reserved -# bits[6:4]: 4 = Die count -# bit7 : 0 = Standard Monolithic DRAM Device -42 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 (reserved) -00 - -# 40 - 47 (reserved) -00 00 00 00 00 00 00 00 - -# 48 - 55 (reserved) -00 00 00 00 00 00 00 00 - -# 56 - 59 (reserved) -00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 71 (reserved) -00 00 00 00 00 00 00 00 - -# 72 - 79 (reserved) -00 00 00 00 00 00 00 00 - -# 80 - 87 (reserved) -00 00 00 00 00 00 00 00 - -# 88 - 95 (reserved) -00 00 00 00 00 00 00 00 - -# 96 - 103 (reserved) -00 00 00 00 00 00 00 00 - -# 104 - 111 (reserved) -00 00 00 00 00 00 00 00 - -# 112 - 116 (reserved) -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -00 - -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -13 12 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -7b 97 |