From f9decbb0c720662d8e71fe221aef55b7ecf76196 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 1 Nov 2022 23:22:55 +0100 Subject: mb/*/*: Remove AMD family14 boards These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu1/BiosCallOuts.c | 58 ---- src/mainboard/pcengines/apu1/Kconfig | 90 ----- src/mainboard/pcengines/apu1/Kconfig.name | 2 - src/mainboard/pcengines/apu1/Makefile.inc | 25 -- src/mainboard/pcengines/apu1/OemCustomize.c | 106 ------ src/mainboard/pcengines/apu1/OptionsIds.h | 36 -- src/mainboard/pcengines/apu1/acpi/buttons.asl | 43 --- src/mainboard/pcengines/apu1/acpi/gpe.asl | 53 --- src/mainboard/pcengines/apu1/acpi/gpio.asl | 25 -- src/mainboard/pcengines/apu1/acpi/leds.asl | 68 ---- src/mainboard/pcengines/apu1/acpi/routing.asl | 315 ------------------ src/mainboard/pcengines/apu1/acpi/sata.asl | 132 -------- src/mainboard/pcengines/apu1/acpi/sleep.asl | 88 ----- src/mainboard/pcengines/apu1/acpi/superio.asl | 3 - src/mainboard/pcengines/apu1/acpi/usb_oc.asl | 148 --------- src/mainboard/pcengines/apu1/board_info.txt | 7 - src/mainboard/pcengines/apu1/bootblock.c | 18 - src/mainboard/pcengines/apu1/buildOpts.c | 44 --- src/mainboard/pcengines/apu1/cmos.default | 2 - src/mainboard/pcengines/apu1/cmos.layout | 31 -- src/mainboard/pcengines/apu1/devicetree.cb | 94 ------ src/mainboard/pcengines/apu1/dsdt.asl | 49 --- src/mainboard/pcengines/apu1/gpio_ftns.c | 29 -- src/mainboard/pcengines/apu1/gpio_ftns.h | 29 -- src/mainboard/pcengines/apu1/irq_tables.c | 88 ----- src/mainboard/pcengines/apu1/mainboard.c | 369 --------------------- src/mainboard/pcengines/apu1/platform_cfg.h | 213 ------------ src/mainboard/pcengines/apu1/romstage.c | 42 --- .../pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex | 234 ------------- .../pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex | 237 ------------- 30 files changed, 2678 deletions(-) delete mode 100644 src/mainboard/pcengines/apu1/BiosCallOuts.c delete mode 100644 src/mainboard/pcengines/apu1/Kconfig delete mode 100644 src/mainboard/pcengines/apu1/Kconfig.name delete mode 100644 src/mainboard/pcengines/apu1/Makefile.inc delete mode 100644 src/mainboard/pcengines/apu1/OemCustomize.c delete mode 100644 src/mainboard/pcengines/apu1/OptionsIds.h delete mode 100644 src/mainboard/pcengines/apu1/acpi/buttons.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/gpe.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/gpio.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/leds.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/routing.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/sata.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/sleep.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/superio.asl delete mode 100644 src/mainboard/pcengines/apu1/acpi/usb_oc.asl delete mode 100644 src/mainboard/pcengines/apu1/board_info.txt delete mode 100644 src/mainboard/pcengines/apu1/bootblock.c delete mode 100644 src/mainboard/pcengines/apu1/buildOpts.c delete mode 100644 src/mainboard/pcengines/apu1/cmos.default delete mode 100644 src/mainboard/pcengines/apu1/cmos.layout delete mode 100644 src/mainboard/pcengines/apu1/devicetree.cb delete mode 100644 src/mainboard/pcengines/apu1/dsdt.asl delete mode 100644 src/mainboard/pcengines/apu1/gpio_ftns.c delete mode 100644 src/mainboard/pcengines/apu1/gpio_ftns.h delete mode 100644 src/mainboard/pcengines/apu1/irq_tables.c delete mode 100644 src/mainboard/pcengines/apu1/mainboard.c delete mode 100644 src/mainboard/pcengines/apu1/platform_cfg.h delete mode 100644 src/mainboard/pcengines/apu1/romstage.c delete mode 100644 src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex delete mode 100644 src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c deleted file mode 100644 index aff72ca0cd..0000000000 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -#include "gpio_ftns.h" - -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; - return AGESA_SUCCESS; -} - -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_RAMINIT) - return AGESA_UNSUPPORTED; - - u8 index = get_spd_offset(); - - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) - die("No SPD data\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig deleted file mode 100644 index 46f4ddec59..0000000000 --- a/src/mainboard/pcengines/apu1/Kconfig +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_PCENGINES_APU1 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_NUVOTON_NCT5104D - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_2048 - select HAVE_SPD_IN_CBFS - select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS - select MEMORY_MAPPED_TPM - -config MAINBOARD_DIR - default "pcengines/apu1" - -config MAINBOARD_PART_NUMBER - default "apu1" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS_ID - string - default "1002,9802" - -config SB800_AHCI_ROM - bool - default n - -choice - prompt "J19 pins 1-10" - default APU1_PINMUX_OFF_C - -config APU1_PINMUX_OFF_C - bool "disable" - -config APU1_PINMUX_GPIO0 - bool "GPIO" - -config APU1_PINMUX_UART_C - bool "UART 0x3e8" - -endchoice - -config UART_C_RS485 - bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C - -choice - prompt "J19 pins 11-20" - default APU1_PINMUX_OFF_D - -config APU1_PINMUX_OFF_D - bool "disable" - -config APU1_PINMUX_GPIO1 - bool "GPIO" - -config APU1_PINMUX_UART_D - bool "UART 0x2e8" - -endchoice - -config UART_D_RS485 - bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D - -config DIMM_SPD_SIZE - default 128 - -endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/Kconfig.name b/src/mainboard/pcengines/apu1/Kconfig.name deleted file mode 100644 index 265f7a6bde..0000000000 --- a/src/mainboard/pcengines/apu1/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_PCENGINES_APU1 - bool "APU1" diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc deleted file mode 100644 index bec5873b02..0000000000 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c -romstage-y += gpio_ftns.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c -ramstage-y += gpio_ftns.c - - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = HYNIX-H5TQ2G83CFR -SPD_SOURCES += HYNIX-H5TQ4G83MFR diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c deleted file mode 100644 index 254947cf8c..0000000000 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 4) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 7) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, - HotplugDisabled, - PcieGen2, - PcieGen2, - AspmL0sL1, 0) - } -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = NULL, -}; - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->GnbConfig.PsppPolicy = 0; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM), - - // APU soldered down memory uses memory CLK0 and CLK1 on CS0 - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - // APU soldered down memory requires different seeds -#define WLSEED 0x08 -#define RXSEED 0x40 - WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; - /* Bank interleaving is not supported on this platform */ - InitPost->MemConfig.EnableBankIntlv = FALSE; -} diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h deleted file mode 100644 index fdd5de0cd1..0000000000 --- a/src/mainboard/pcengines/apu1/OptionsIds.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - - -#endif diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl deleted file mode 100644 index aa235f9f79..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/buttons.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (BTNS) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionInputOnly, - "\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {187} - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-keys-polled"}}, - Package () {"poll-interval", 100}, - Package () {"autorepeat", 1} - } - }) - - Device (BTN1) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* BTN_1 is 0x101 in linux/input.h */ - Package () {"linux,code", 257}, - Package () {"linux,input-type", 1}, - /* labeled S1 on the board, MODESW in the gpio header files */ - Package () {"label", "switch1"}, - Package () {"gpios", Package () {^^BTNS, 0, 0, 1 /* low-active */}}, - } - }) - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl deleted file mode 100644 index 705abf17f6..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu1/acpi/gpio.asl b/src/mainboard/pcengines/apu1/acpi/gpio.asl deleted file mode 100644 index 20bbf60a56..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/gpio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (GPIO) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - /* ACPI_MMIO_BASE + gpio offset */ - Memory32Fixed(ReadWrite, 0xFED80100, 0x0000100) - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-sb8xx"}}, - } - }) - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl deleted file mode 100644 index 128e0f1f24..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/leds.asl +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/ - */ - -Scope (\_SB.PCI0.SBUS) -{ - Device (LEDS) - { - Name (_HID, "PRP0001") - - Name (_CRS, ResourceTemplate () { - GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, - "\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {189, 190, 191} - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"compatible", Package () {"gpio-leds"}}, - } - }) - - Device (LED1) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* - * From Linux Documentation/leds/leds-class.txt: - * LED Device Naming - * Is currently of the form: - * "devicename:colour:function" - */ - Package () {"label", "apu1:green:led1"}, - Package () {"gpios", Package () {^^LEDS, 0, 0, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } }) } - - Device (LED2) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"label", "apu1:green:led2"}, - Package () {"gpios", Package () {^^LEDS, 0, 1, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } - }) - } - - Device (LED3) - { - Name (_HID, "PRP0001") - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"label", "apu1:green:led3"}, - Package () {"gpios", Package () {^^LEDS, 0, 2, 1 /* low-active */}}, - Package () {"default-state", "keep"}, - } - }) - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl deleted file mode 100644 index deef1ec22c..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ /dev/null @@ -1,315 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ - Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* OHCI, dev 18, 19, 22 func 0 - * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: PCIe */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl deleted file mode 100644 index 6d9ff03005..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (P0IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (P1IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (P2IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (P3IS > 0) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (\_SB.P0IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P0PR = 1 - } - - if (\_SB.P1PR) { - if (\_SB.P1IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P1PR = 1 - } - - if (\_SB.P2PR) { - if (\_SB.P2IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P2PR = 1 - } - - if (\_SB.P3PR) { - if (\_SB.P3IS > 0) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - \_SB.P3PR = 1 - } - } -} diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl deleted file mode 100644 index 3b6fd02055..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (Arg0 == 3){ - URRE = 0 - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*CSSM = 1 - SSEN = 1*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\_SB.SBRI <= 0x13) { - * \_SB.PWDE = 0 - *} - */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - HPDE = 1 - - /* Restore PCIRST# so it resets USB */ - if (Arg0 == 3){ - URRE = 1 - } - - /* Arbitrarily clear PciExpWakeStatus */ - Local1 = PWST - PWST = Local1 - - /* if (DeRefOf(WKST [0])) { - * WKST [1] = 0 - * } else { - * WKST [1] = Arg0 - * } - */ - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/pcengines/apu1/acpi/superio.asl b/src/mainboard/pcengines/apu1/acpi/superio.asl deleted file mode 100644 index d2d8a44c23..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl deleted file mode 100644 index e4ed275617..0000000000 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -Method(UCOC, 0) { - Sleep(20) - CMTI = 0x13 - GPSL = 0 -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If (UOM0 <= 9) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if (GPB0 == PLC0) { - PLC0 = ~PLC0 - \_SB.PT0D = PLC0 - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (UOM1 <= 9) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (GPB1 == PLC1) { - PLC1 = ~PLC1 - \_SB.PT1D = PLC1 - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (UOM2 <= 9) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (GPB2 == PLC2) { - PLC2 = ~PLC2 - \_SB.PT2D = PLC2 - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (UOM3 <= 9) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (GPB3 == PLC3) { - PLC3 = ~PLC3 - \_SB.PT3D = PLC3 - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (UOM4 <= 9) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (GPB4 == PLC4) { - PLC4 = ~PLC4 - \_SB.PT4D = PLC4 - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (UOM5 <= 9) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (GPB5 == PLC5) { - PLC5 = ~PLC5 - \_SB.PT5D = PLC5 - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (UOM6 <= 9) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (GPB6 == PLC6) { - PLC6 = ~PLC6 - \_SB.PT6D = PLC6 - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (UOM7 <= 9) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (GPB7 == PLC7) { - PLC7 = ~PLC7 - \_SB.PT7D = PLC7 - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (UOM8 <= 9) { - Scope (\_GPE) { - Method (_L17) { - if (G8IS == PLC8) { - PLC8 = ~PLC8 - \_SB.PT8D = PLC8 - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (UOM9 <= 9) { - Scope (\_GPE) { - Method (_L0E) { - if (G9IS == 0) { - \_SB.PT9D = 1 - } - } - } -} diff --git a/src/mainboard/pcengines/apu1/board_info.txt b/src/mainboard/pcengines/apu1/board_info.txt deleted file mode 100644 index 68d347d93a..0000000000 --- a/src/mainboard/pcengines/apu1/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Board name: apu1 -Board URL: http://www.pcengines.ch/apu1d4.htm -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c deleted file mode 100644 index 2016e7b6fa..0000000000 --- a/src/mainboard/pcengines/apu1/bootblock.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - -void bootblock_mainboard_early_init(void) -{ - if (CONFIG_UART_FOR_CONSOLE == 1) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c deleted file mode 100644 index 255893833c..0000000000 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Select the CPU family */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE - -/* Agesa optional capabilities selection */ -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_ENABLE_DMI TRUE - -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE - -/* Agesa configuration values selection */ -#include - -/* Include the files that instantiate the configuration definitions */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/* Instantiate all solution relevant data */ -#include diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default deleted file mode 100644 index 06b04332a2..0000000000 --- a/src/mainboard/pcengines/apu1/cmos.default +++ /dev/null @@ -1,2 +0,0 @@ -boot_option=Fallback -debug_level=Debug diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout deleted file mode 100644 index e36dd6bd61..0000000000 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ /dev/null @@ -1,31 +0,0 @@ -entries - -# -0 384 r 0 reserved_memory -384 4 r 0 reboot_bits -# leave 3 bits to make checksummed area start byte-aligned -392 1 e 2 boot_option -400 4 e 4 debug_level -# leave 7 bits to make checksummed area end byte-aligned -408 16 h 0 check_sum - -enumerations - -#