diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-16 00:54:30 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-17 16:27:52 +0000 |
| commit | 1952d13a414229f1867a8a9c00fc07df07d7042c (patch) | |
| tree | a3528d580f78b7b856dde5e8d9ca980fa1d6d07f /src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | |
| parent | 0010b89c67354dd4dda1417e6fc990cc3b82f0d4 (diff) | |
nb/amd/pi/00730F01: restructure chip ops
Since this chip is a SoC and also to bring the chipset devicetree more
in line with the chipset devicetree of Sandy Bridge, merge the chip
operations of the northbridge's root complex and the northbridge itself
into one chip operations structure and use it at the top level of the
devicetree.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb')
| -rw-r--r-- | src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index dcff5abb71..5c169208b9 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 |