diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-04 08:49:21 +0000 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-07 12:07:15 +0000 |
| commit | 869ac71483616cd363170cdf2cf5d4ce1965a2a1 (patch) | |
| tree | e386332a5385466ae8b067fec7a5291be8503ddd /src/mainboard/pcengines/apu2/OemCustomize.c | |
| parent | 7daf3cd32e259889c0cb419b4440422649d82266 (diff) | |
Revert "mb/pcengines/apu2: add reset logic for PCIe slots"
This reverts commit c04871a398ca945b42fde0867572094c38f6f92c.
Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.
Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu2/OemCustomize.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/OemCustomize.c | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 78ff99459c..7d943c8bdf 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -4,16 +4,6 @@ #include <AGESA.h> #include <northbridge/amd/agesa/state_machine.h> -#define PCIE_NIC_RESET_ID 1 - -#if CONFIG(BOARD_PCENGINES_APU2) -#define PCIE_GFX_RESET_ID 55 -#define PCIE_PORT3_RESET_ID 51 -#else -#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID -#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID -#endif - static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -23,7 +13,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_PORT3_RESET_ID, + 0x01, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ @@ -35,7 +25,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x02, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ @@ -47,7 +37,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x03, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ @@ -59,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x04, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ @@ -71,7 +61,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_GFX_RESET_ID, + 0x05, 0) } }; |