From 869ac71483616cd363170cdf2cf5d4ce1965a2a1 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Sat, 4 Apr 2020 08:49:21 +0000 Subject: Revert "mb/pcengines/apu2: add reset logic for PCIe slots" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit c04871a398ca945b42fde0867572094c38f6f92c. Reason for revert: Many apu2 users reported issues with PCIe modules detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught by 3mdeb validation stands and hardware configuration. Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu2/OemCustomize.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'src/mainboard/pcengines/apu2/OemCustomize.c') diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 78ff99459c..7d943c8bdf 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -4,16 +4,6 @@ #include #include -#define PCIE_NIC_RESET_ID 1 - -#if CONFIG(BOARD_PCENGINES_APU2) -#define PCIE_GFX_RESET_ID 55 -#define PCIE_PORT3_RESET_ID 51 -#else -#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID -#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID -#endif - static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -23,7 +13,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_PORT3_RESET_ID, + 0x01, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ @@ -35,7 +25,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x02, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ @@ -47,7 +37,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x03, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ @@ -59,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_NIC_RESET_ID, + 0x04, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ @@ -71,7 +61,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, - PCIE_GFX_RESET_ID, + 0x05, 0) } }; -- cgit v1.2.3