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authorSridhar Siricilla <sridhar.siricilla@intel.com>2022-07-06 14:39:01 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-07-06 19:21:14 +0000
commit22369a1fc2042868a4db009290056a266fc1b369 (patch)
tree8b95862226267c225200b5a3c8291e1753f539ea /src/mainboard/pcengines/apu1
parent8e10a4826a8fe83292a084450cf1b905ac832edd (diff)
soc/intel/common: Update the comment on CSE Region layout
The comment indicates CSE's data partition is placed after BP2. But, it was place after BP1.So, the patch updates the comment to reflect the CSE Region layout correctly. TEST=Build the code for Brya and didn't notice any compilation errors Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
0 files changed, 0 insertions, 0 deletions