diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-11 17:22:23 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-23 21:34:55 +0100 |
| commit | 780935687d74f89a25a9c58952314be6af61c348 (patch) | |
| tree | 193897842085f03675cb6b97e1f9ca523abb7a83 /src/mainboard/pcengines/apu1/devicetree.cb | |
| parent | 8c190f3518d504d904692e93e7881c379b89f542 (diff) | |
pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/devicetree.cb')
| -rw-r--r-- | src/mainboard/pcengines/apu1/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 5f6f9c9ee7..a0a6a35f52 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -87,6 +87,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 16.0 on end # OHCI USB 10-13 device pci 16.2 on end # EHCI USB 10-13 register "gpp_configuration" = "0" + register "disconnect_pcib" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 # end # device pci 18.0 |