From 780935687d74f89a25a9c58952314be6af61c348 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 11 Nov 2014 17:22:23 +0200 Subject: pcengines/apu1: Implement board GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/pcengines/apu1/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/pcengines/apu1/devicetree.cb') diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 5f6f9c9ee7..a0a6a35f52 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -87,6 +87,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 16.0 on end # OHCI USB 10-13 device pci 16.2 on end # EHCI USB 10-13 register "gpp_configuration" = "0" + register "disconnect_pcib" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 # end # device pci 18.0 -- cgit v1.2.3