mb/google/brya: Update PMC Descriptor for Alder lake A0(0x906a0) silicon

The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons.

BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if
not updated.

coreboot logs appear as below with this patch:

On First boot after flashing the image:

	coreboot-coreboot-unknown.9999.4589c0f Wed Jun  9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
	CPU: Genuine Intel(R) 0000
	CPU: ID 906a0, Alderlake Platform, ucode: 0000001a
	..
	FMAP: Found "FLASH" version 1.1 at 0x1804000.
	FMAP: base = 0x0 size = 0x2000000 #areas = 32
	FMAP: area SI_DESC found @ 0 (4096 bytes)
	SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
	Erasing flash addr 0 + 4 KiB
	Update of PMC Descriptor successful, trigger GLOBAL RESET

Next boot after GLOBAL RESET:

	coreboot-coreboot-unknown.9999.4589c0f Wed Jun  9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
	..
	FMAP: area SI_DESC found @ 0 (4096 bytes)
	SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
	Update of PMC Descriptor is not required!
	VBOOT: Loading verstage.
	..
	CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions