diff options
author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-07-28 18:55:40 +0200 |
---|---|---|
committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-07-28 18:18:00 +0000 |
commit | 660dd0007953916d82ff66c238dc30e610f45c08 (patch) | |
tree | 26678423e59bf0a5648f1323d52f6a552209c5b6 /src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb | |
parent | 48b24252f647f96d7c127a3e00658fb47c41474a (diff) |
mainboard/opencellular/rotundu: Add supabrck EMMC support
Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb')
-rw-r--r-- | src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb index a31a001657..df089229f4 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/fsp_baytrail register "PcdMrcInitSPDAddr1" = "0xa0" register "PcdMrcInitSPDAddr2" = "0xa2" register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_DISABLED" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" register "PcdGttSize" = "GTT_SIZE_DEFAULT" @@ -53,7 +53,7 @@ chip soc/intel/fsp_baytrail device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time device pci 15.0 off end # 8086 0F28 - LP Engine Audio device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time + device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time device pci 18.0 on end # 8086 0F40 - SIO - DMA device pci 18.1 on end # 8086 0F41 - I2C Port 1 device pci 18.2 off end # 8086 0F42 - I2C Port 2 |