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authorAngel Pons <th3fanbus@gmail.com>2022-05-02 16:58:39 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-04 13:11:21 +0000
commit623e2b351c80d2086af3e9dbd523dd6e9d06339b (patch)
tree4c497f00b7e1fdf7bcc2e8cae0f3e67f78200206 /src/mainboard/ocp/tiogapass/acpi
parentf0ed846cfce843965f191e56ba01b35d8c9195b0 (diff)
mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines
Use common ASL defines for POST code handling. Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/tiogapass/acpi')
-rw-r--r--src/mainboard/ocp/tiogapass/acpi/platform.asl8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl
index 9f51fdf12f..782d2cd26f 100644
--- a/src/mainboard/ocp/tiogapass/acpi/platform.asl
+++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl
@@ -21,13 +21,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
APMS, 8 // APM status
}
-/* Port 80 POST */
-OperationRegion (DBG0, SystemIO, 0x80, 0x02)
-Field (DBG0, ByteAcc, Lock, Preserve)
-{
- IO80, 8,
- IO81, 8
-}
+#include <arch/x86/acpi/post.asl>
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.