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authorJonathan Zhang <jonzhang@fb.com>2020-08-21 13:32:20 -0700
committerAngel Pons <th3fanbus@gmail.com>2020-08-28 17:44:46 +0000
commitd5f24dd99bb245a6de2d8ca86bfabda05bdb82d1 (patch)
tree7e6fa9b7af762ee6915795fa257bb7ea61687908 /src/mainboard/ocp/deltalake
parent0f51ff72e444b58ee89f39234b6b3609a445fe15 (diff)
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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