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| author | Morgan Jang <Morgan_Jang@wiwynn.com> | 2020-05-25 12:23:59 +0800 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-07-16 13:07:31 +0000 |
| commit | b29d16fc8a1e15a9a5e7f5b389019b7593d42d02 (patch) | |
| tree | c4b732fc6dd19f0a9b67f48eda158bc22b456572 /src/mainboard/ocp/deltalake/devicetree.cb | |
| parent | b8d0d089b307a8e40f12af82d0191d52f8752b37 (diff) | |
mb/ocp/deltalake: Config PCH PCIe ports in devicetree
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/mainboard/ocp/deltalake/devicetree.cb')
| -rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f1b201d5f4..cc17e06f6c 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -39,6 +39,12 @@ chip soc/intel/xeon_sp/cpx register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS + # configure PCH PCIe port + register "pch_pci_port[8]" = "{ + .ForceEnable = 0x1, + .PortLinkSpeed = PcieAuto, + }" + device cpu_cluster 0 on device lapic 0 on end end |