diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2008-02-20 17:41:38 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2008-02-20 17:41:38 +0000 |
commit | f327d9f9540971518e1661e1f50d30ffa6b74173 (patch) | |
tree | 51e84712bcaf920a99413e46dd9d255d4278d5c9 /src/mainboard/nvidia/l1_2pvv/mptable.c | |
parent | 8eff1e3d0419f42684fc8a63e1dd0a84eb7e9b50 (diff) |
Route device IRQ through PCI bridge instead in mptable.
Don't enable pin0 for ioapic of io-4.
1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
for device under them in mptable.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nvidia/l1_2pvv/mptable.c')
-rw-r--r-- | src/mainboard/nvidia/l1_2pvv/mptable.c | 120 |
1 files changed, 64 insertions, 56 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index 1402d1ebd8..aa7c82668e 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -39,6 +39,7 @@ void *smp_write_config_table(void *v) unsigned sbdn; int i,j; + unsigned char apicpin[4]; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -65,8 +66,8 @@ void *smp_write_config_table(void *v) /*Bus: Bus ID Type*/ /* define bus and isa numbers */ - for(j= 0; j < 256 ; j++) { - if(m->bus_type[j]) + for (j = 0; j < 256 ; j++) { + if (m->bus_type[j]) smp_write_bus(mc, j, "PCI "); } smp_write_bus(mc, m->bus_isa, "ISA "); @@ -77,38 +78,43 @@ void *smp_write_config_table(void *v) struct resource *res; uint32_t dword; - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); - } + + /* Initialize interrupt mapping*/ + dword = pci_read_config32(dev, 0x74); + dword &= ~(1<<15); + dword |= 1<<2; + pci_write_config32(dev, 0x74, dword); dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword); dword = 0x81001a00; pci_write_config32(dev, 0x80, dword); - dword = 0xd00012d2; + dword = 0xd00012d2; pci_write_config32(dev, 0x84, dword); } - if(m->bus_mcp55b[0]) { - dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x1,0)); + if (m->bus_mcp55b) { + dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { + if (res) smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base); - } + dword = 0x43c60000; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword); dword = 0x81000000; pci_write_config32(dev, 0x80, dword); - dword = 0xd00002d0; + dword = 0xd00002d0; pci_write_config32(dev, 0x84, dword); } @@ -116,8 +122,8 @@ void *smp_write_config_table(void *v) } } - - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); @@ -131,63 +137,65 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } +//Slot PCIE + for (j = 2; j < 8; j++) { + device_t dev; + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); + if (!dev || !dev->enabled) + continue; + for (i = 0; i < 4; i++) + apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4; + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); } - for(j=0; j<2; j++) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x06+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } - - if(m->bus_mcp55b[0]) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21 - - - for(j=7; j>=2; j--) { - if(!m->bus_mcp55b[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[j], (0x00<<2)|i, m->apicid_mcp55b, 0x10 + (2+j+i+4-m->sbdnb%4)%4); - } +//Slot PCI 32 + { + device_t dev; + dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); + if (dev && dev->enabled) { + for (i = 0; i < 4; i++) + apicpin[i] = 0x10 + (2+i)%4; + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); } } -#if 1 - if(m->bus_pcix[0]) { + if (m->bus_mcp55b) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21 - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[2], (4<<2)|i, m->apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 - } + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[1], (4<<2)|i, m->apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 + //Slot PCIE + for (j = 2; j < 8; j++) { + device_t dev; + dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); + if (!dev || !dev->enabled) + continue; + for (i = 0; i < 4; i++) { + apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4; + } + smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin); } + } -#endif /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); |