diff options
author | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:57:53 +0000 |
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committer | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:57:53 +0000 |
commit | baec0346b028d59c4ec226961d977bec0c57ed7e (patch) | |
tree | f1ee11002f329595b1838667d9b3aac5aa617cf7 /src/mainboard/nokia/ip530/devicetree.cb | |
parent | b297b4901a5e7dd0aa037b184329a0e96722149e (diff) |
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nokia/ip530/devicetree.cb')
-rw-r--r-- | src/mainboard/nokia/ip530/devicetree.cb | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 3cfbc8fb0f..ac6d78ed75 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -28,6 +28,17 @@ chip northbridge/intel/i440bx # Northbridge device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + device pci f.0 on + chip southbridge/ti/pci1x2x + device pci 00.0 on + + end + register "cltr" = "0x40" + register "bcr" = "0x7c0" + register "scr" = "0x08449060" + register "mrr" = "0x00007522" + end + end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) |