diff options
| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-04 14:26:26 -0600 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-05 21:53:55 +0100 |
| commit | 7ad4dc5e9914e927a827ce48a030d2d04e7ec792 (patch) | |
| tree | 1a279d488f9730ff954a7783dfde95c275c1a09c /src/mainboard/msi | |
| parent | d502dc092a26726472fc5871c77ebff192be4cb8 (diff) | |
src/amd: Add common definition of AMD ACPI MMIO address
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/msi')
| -rw-r--r-- | src/mainboard/msi/ms7721/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 4aeb1ec17b..9ce47f2196 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -30,6 +30,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pnp_def.h> +#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smbus.h> @@ -41,8 +42,7 @@ #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO 0xFED80000 -#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SUPERIO_ADDRESS 0x4e |