mb/*/*: Drop AMDFAM10 mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 271 deletions

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
deleted file mode 100644
index 4658d75427..0000000000
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <spd.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <delay.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <cpu/x86/bist.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <southbridge/amd/common/reset.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-
-#include "cpu/amd/quadcore/quadcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
-	pci_devfn_t dev;
-
-	/* Find the device. */
-	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
-				       PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
-	return (dev >> 15) & 0x1f;
-}
-
-#define MCP55_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-
-static void sio_setup(void)
-{
-	u32 dword;
-	u8 byte;
-
-	byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
-	dword |= (1 << 0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
-}
-
-static const u8 spd_addr[] = {
-	//first node
-	RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-	//second node
-	RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-};
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	struct sys_info *sysinfo = get_sysinfo();
-	u32 bsp_apicid = 0, val, wants_reset;
-	u8 reg;
-	msr_t msr;
-
-	timestamp_init(timestamp_get());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		set_bsp_node_CHtExtNodeCfgEn();
-		enumerate_ht_chain();
-		sio_setup();
-	}
-
-	post_code(0x30);
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	post_code(0x32);
-
-	pnp_enter_conf_state(SERIAL_DEV);
-	/* We have 24MHz input. */
-	reg = pnp_read_config(SERIAL_DEV, 0x24);
-	pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
-	pnp_exit_conf_state(SERIAL_DEV);
-
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-	printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	/* Setup sysinfo defaults */
-	set_sysinfo_in_ram(0);
-
-	update_microcode(val);
-
-	post_code(0x33);
-
-	cpuSetAMDMSR(0);
-	post_code(0x34);
-
-	amd_ht_init(sysinfo);
-	post_code(0x35);
-
-	/* Setup nodes PCI space and start core 0 AP init. */
-	finalize_node_setup(sysinfo);
-	printk(BIOS_DEBUG, "finalize_node_setup done\n");
-
-	/* Setup any mainboard PCI settings etc. */
-	printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
-	setup_mb_resource_map();
-	printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
-	post_code(0x36);
-
-	/* wait for all the APs core0 started by finalize_node_setup. */
-	/* FIXME: A bunch of cores are going to start output to serial at once.
-	 * It would be nice to fixup prink spinlocks for ROM XIP mode.
-	 * I think it could be done by putting the spinlock flag in the cache
-	 * of the BSP located right after sysinfo.
-	 */
-	wait_all_core0_started();
-
-#if CONFIG(LOGICAL_CPUS)
-	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk(BIOS_DEBUG, "start_other_cores()\n");
-	start_other_cores(bsp_apicid);
-	post_code(0x37);
-	printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
-	wait_all_other_cores_started(bsp_apicid);
-#endif
-
-	post_code(0x38);
-
-#if CONFIG(SET_FIDVID)
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
-	/* FIXME: The sb fid change may survive the warm reset and only
-	 * need to be done once.*/
-	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
-	post_code(0x39);
-
-	if (!warm_reset_detect(0)) {			// BSP is node 0
-		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
-	} else {
-		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
-	}
-
-	post_code(0x3A);
-
-	/* show final fid and vid */
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
-	init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
-	wants_reset = mcp55_early_setup_x();
-
-	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	if (wants_reset)
-		printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
-
-	post_code(0x3B);
-
-	/* It's the time to set ctrl in sysinfo now; */
-	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	post_code(0x3D);
-
-	printk(BIOS_DEBUG, "enable_smbus()\n");
-	enable_smbus();
-
-	post_code(0x40);
-
-	raminit_amdmct(sysinfo);
-
-	cbmem_initialize_empty();
-	post_code(0x41);
-
-	amdmct_cbmem_store_info(sysinfo);
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- *	This routine is called every time a non-coherent chain is processed.
- *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- *	swap list. The first part of the list controls the BUID assignment and the
- *	second part of the list provides the device to device linking.  Device orientation
- *	can be detected automatically, or explicitly.  See documentation for more details.
- *
- *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- *	based on each device's unit count.
- *
- * Parameters:
- *	@param[in]  node   = The node on which this chain is located
- *	@param[in]  link   = The link on the host for this chain
- *	@param[out] List   = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
-	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
-	/* If the BUID was adjusted in early_ht we need to do the manual override */
-	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
-		if ((node == 0) && (link == 0)) {	/* BSP SB link */
-			*List = swaplist;
-			return 1;
-		}
-	}
-
-	return 0;
-}