mb/msi/ms7d25: Configure PCIe Root Ports

Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).

TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 103 insertions, 31 deletions

diff --git a/src/mainboard/msi/ms7d25/gpio.h b/src/mainboard/msi/ms7d25/gpio.h
index d4694eab6a..74a2d93453 100644
--- a/src/mainboard/msi/ms7d25/gpio.h
+++ b/src/mainboard/msi/ms7d25/gpio.h
@@ -2,6 +2,25 @@
 
 #include <soc/gpio.h>
 
+/* GPIO Native Function Virtual Wire Enable */
+#define PAD_CFG_GPIO_NAF_VWE		(1 << 27)
+
+/*
+ * Do not program the CLKREQ signals in coreboot to let FSP detect and
+ * configure CLKREQ pads for PCIe ports. Otherwise the CLKREQ pads are
+ * reprogrammed by FSP despite having GpioOverride=1 in the following manner:
+ *
+ * GPIO (reset) -> (CLKREQ (coreboot, configure pads) ->
+ * GPIO input (FSP, detect) -> CLKREQ (FSP).
+ *
+ * Also if GpioOverride=1 the NAF_VME bit is not set for virtual wire GPIOs
+ * that require it, e.g. the CPU PCIe CLKREQ bus. The pads that should not be
+ * touched by coreboot are left commented in this file for reference. CLKREQ
+ * reprogramming caused undefined behavior when ASPM and Clock PM was being
+ * enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed
+ * a lot of exceptions and simply halted).
+ */
+
 /* Pad configuration was generated automatically using intelp2m utility */
 static const struct pad_config gpio_table[] = {
 
@@ -121,10 +140,11 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
 	/* GPP_J7 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI),
+	/* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 	/* GPP_J8 - SRCCLKREQ16# */
-	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
 	/* GPP_J9 - SRCCLKREQ17# */
-	PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
 	/* GPP_J10 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
 	/* GPP_J11 - GPIO */
@@ -133,25 +153,28 @@ static const struct pad_config gpio_table[] = {
 	/* vGPIO controls certain features like CNVi, include the definitions as well */
 
 	/* ------- GPIO Group vGPIO ------- */
-	_PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),	/* GPIO */
-	_PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
-	_PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),	/* GPIO */
+	/* CNVi BT Enable, TX = 1 */
+	_PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
+	/* CNVi BT host wake */
+	_PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	/* CNVi BT on USB, TX = 1 */
+	_PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
 	_PAD_CFG_STRUCT(VGPIO_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
-	_PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_10 */
-	_PAD_CFG_STRUCT(VGPIO_11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_11 */
-	_PAD_CFG_STRUCT(VGPIO_12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_12 */
-	_PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_13 */
+	_PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_TXD */
+	_PAD_CFG_STRUCT(VGPIO_11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_RXD */
+	_PAD_CFG_STRUCT(VGPIO_12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_CTS# */
+	_PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_RTS# */
 	_PAD_CFG_STRUCT(VGPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
-	_PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_22 */
-	_PAD_CFG_STRUCT(VGPIO_23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_23 */
-	_PAD_CFG_STRUCT(VGPIO_24, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_24 */
-	_PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_25 */
+	_PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_TXD */
+	_PAD_CFG_STRUCT(VGPIO_23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_RXD */
+	_PAD_CFG_STRUCT(VGPIO_24, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_CTS# */
+	_PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_RTS# */
 	_PAD_CFG_STRUCT(VGPIO_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 	_PAD_CFG_STRUCT(VGPIO_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
@@ -162,14 +185,15 @@ static const struct pad_config gpio_table[] = {
 	_PAD_CFG_STRUCT(VGPIO_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
 
 	/* ------- GPIO Group vGPIO_0 ------- */
-	_PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_USB_0 */
-	_PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_USB_1 */
-	_PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_USB_2 */
-	_PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* VGPIO_USB_3 */
-	_PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_USB_8 */
-	_PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_USB_9 */
-	_PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_USB_10 */
-	_PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0),	/* VGPIO_USB_11 */
+	/* These are Virtual USB OC pins */
+	_PAD_CFG_STRUCT(VGPIO_USB_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_0 */
+	_PAD_CFG_STRUCT(VGPIO_USB_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_1 */
+	_PAD_CFG_STRUCT(VGPIO_USB_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_2 */
+	_PAD_CFG_STRUCT(VGPIO_USB_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_3 */
+	_PAD_CFG_STRUCT(VGPIO_USB_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_8 */
+	_PAD_CFG_STRUCT(VGPIO_USB_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_9 */
+	_PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_10 */
+	_PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_11 */
 
 	/* ------- GPIO Community 1 ------- */
 
@@ -249,22 +273,23 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
 	/* GPP_H1 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
+	/* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 	/* GPP_H2 - SRCCLKREQ8# */
-	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
 	/* GPP_H3 - SRCCLKREQ9# */
-	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
 	/* GPP_H4 - SRCCLKREQ10# */
-	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 	/* GPP_H5 - SRCCLKREQ11# */
-	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 	/* GPP_H6 - SRCCLKREQ12# */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 	/* GPP_H7 - SRCCLKREQ13# */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 	/* GPP_H8 - SRCCLKREQ14# */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 	/* GPP_H9 - SRCCLKREQ15# */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	// PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 
 	/* GPP_H10 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
@@ -412,6 +437,52 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_C23 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
 
+	/* TODO: move VW programming to soc directory and make it dependent on FSP settings? */
+	/* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
+	/* CPU PCIe 6.0 CLKREQ virtual wire message bus */
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+
+	/* CPU PCIe 1.0 CLKREQ virtual wire message bus */
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+	// _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0),
+
 	/* ------- GPIO Community 4 ------- */
 
 	/* ------- GPIO Group GPP_S ------- */
@@ -562,8 +633,9 @@ static const struct pad_config gpio_table[] = {
 
 	/* ------- GPIO Group GPP_D ------- */
 
-	/* GPP_D0 - GPIO */
-	PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, PLTRST, OFF, ACPI),
+	/* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
+	/* GPP_D0 - CLKREQ0# */
+	// PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
 	/* GPP_D1 - GPIO */
 	PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
 	/* GPP_D2 - GPIO */