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authorRaul E Rangel <rrangel@chromium.org>2021-12-16 10:43:26 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-12-18 12:23:21 +0000
commit78ee4889dc3213d14db1074c55ae367a1ffac54a (patch)
treebad846eb9f278e1095c018b7524e18e6a517ae18 /src/mainboard/msi/ms7721/Kconfig
parent0040bba74fd6e47fd7e01a31eab4d2b0bf05d675 (diff)
soc/amd/cezanne/acpi: Add support for RTC workaround
The RTC on Cezanne is an unstable wake source when the system is in S0i3. We instead need to use an internal timer that triggers a GPIO that acts as a wake source. This change provides the ACPI necessary to allow the OS to manage the wake source. BUG=b:209705576 TEST=Boot guybrush with this patch and several OS patches. Verified the OS sets the correct wake bit, the system correctly suspends and resumes, and the wake source is correctly accounted for. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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