diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-12 14:51:49 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2023-02-04 01:42:39 +0000 |
| commit | b5df65a9aaee50421913ace6d7a4b35e0ddff676 (patch) | |
| tree | aa885e29c4e724f4fb583bca5c93fe1243e95da2 /src/mainboard/msi/ms7707 | |
| parent | 9ce7935b490830a709c62e271bf269801520ec29 (diff) | |
mb/*: Replace SNB PCI devices with references from chipset.cb
Removing default on/off from mainboard devicetrees is left as a follow-up.
Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/msi/ms7707')
| -rw-r--r-- | src/mainboard/msi/ms7707/devicetree.cb | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index e0fbc1ab34..a2c0237209 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -2,9 +2,9 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1462 0x7707 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 off end # Internal graphics + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" @@ -17,24 +17,24 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" # 0x28 register "multi_function_register_1" = "0xc0" # 0x29 @@ -94,10 +94,10 @@ chip northbridge/intel/sandybridge end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end |