diff options
author | Mike Banon <mikebdp2@gmail.com> | 2020-02-13 16:29:11 +0000 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 13:55:18 +0000 |
commit | 6ed9df448b4d025a4caa01b594fca90724eef691 (patch) | |
tree | 551d09700056b14b5f1da551c1b8e537aaad8c65 /src/mainboard/lippert/toucan-af/bootblock.c | |
parent | c896df7f158cf759906f4f164330fb552bbe0fec (diff) |
mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lippert/toucan-af/bootblock.c')
-rw-r--r-- | src/mainboard/lippert/toucan-af/bootblock.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/lippert/toucan-af/bootblock.c b/src/mainboard/lippert/toucan-af/bootblock.c new file mode 100644 index 0000000000..39b108e6dc --- /dev/null +++ b/src/mainboard/lippert/toucan-af/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} |