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authorAndrey Korolyov <andrey@xdel.ru>2017-08-16 17:53:40 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-12-19 21:15:48 +0000
commit60d9ce3937f15cff56218a08d9ccfd5d0358fbfc (patch)
treebb74993aabd2ed13f087b4d2f2256b4c6b3a62e9 /src/mainboard/lenovo/z61t/acpi
parent1d2aed2367b83cd2a0651fa85756c5f394c136f9 (diff)
mainboard/lenovo: add Lenovo Z61t laptop
This platform shares most hardware components with first-gen Core Lenovo laptops such as T60/X60, with much smaller EEPROM size as one of notable differences. The port features Intel graphics, ATI-based version should work with vendor VBIOS. Tested peripherals: - sleep/resume, - USB ports, - ACPI Fn key bindings/volume buttons, - backlight control, - ethernet, - wireless (under Linux), - sound/beep, - dock handling, - serial via dock. Untested peripherals: - IrDA, - parallel port, - PCMCIA, - S-Video port, - modem, - FP reader (should just work), - IEEE1394. Linux 3.16 works with native gfxinit perfectly, with Intel VBIOS console sometimes displays nothing when i915 framebuffer is used. Windows 7 has an interrupt assignment issue with iw3945, otherwise tested stuff is fine. Change-Id: I84c89cc47d3db126d827f92d50270954bc42f224 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/21019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/z61t/acpi')
-rw-r--r--src/mainboard/lenovo/z61t/acpi/dock.asl93
-rw-r--r--src/mainboard/lenovo/z61t/acpi/ec.asl17
-rw-r--r--src/mainboard/lenovo/z61t/acpi/gpe.asl27
-rw-r--r--src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl58
-rw-r--r--src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl41
-rw-r--r--src/mainboard/lenovo/z61t/acpi/mainboard.asl0
-rw-r--r--src/mainboard/lenovo/z61t/acpi/platform.asl81
-rw-r--r--src/mainboard/lenovo/z61t/acpi/superio.asl0
-rw-r--r--src/mainboard/lenovo/z61t/acpi/video.asl32
9 files changed, 349 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/z61t/acpi/dock.asl b/src/mainboard/lenovo/z61t/acpi/dock.asl
new file mode 100644
index 0000000000..5085b29fb3
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/dock.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "smi.h"
+
+Scope (\_SB)
+{
+ OperationRegion (DLPC, SystemIO, 0x164c, 1)
+ Field(DLPC, ByteAcc, NoLock, Preserve)
+ {
+ , 3,
+ DSTA, 1,
+ }
+
+ Device(DOCK)
+ {
+ Name(_HID, "ACPI0003")
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB } )
+
+ Method(_DCK, 1, NotSerialized)
+ {
+ if (Arg0) {
+ Sleep(250)
+ /* connect dock */
+ TRAP(SMI_DOCK_CONNECT)
+ } else {
+ /* disconnect dock */
+ TRAP(SMI_DOCK_DISCONNECT)
+ }
+
+ Xor(Arg0, DSTA, Local0)
+ Return (Local0)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (DSTA)
+ }
+ }
+}
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ OperationRegion(PMH7, SystemIO, 0x15e0, 0x10)
+ Field(PMH7, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x0c),
+ PIDX, 8,
+ Offset(0x0e),
+ PDAT, 8,
+ }
+
+ IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x61),
+ DPWR, 1,
+ }
+
+ Method(_Q18, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 3)
+ }
+
+ Method(_Q37, 0, NotSerialized)
+ {
+ if (DPWR) {
+ Notify(\_SB.DOCK, 0)
+ } else {
+ Notify(\_SB.DOCK, 3)
+ }
+ }
+
+ Method(_Q50, 0, NotSerialized)
+ {
+ if (\_SB.DOCK._STA()) {
+ Notify(\_SB.DOCK, 1)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/z61t/acpi/ec.asl b/src/mainboard/lenovo/z61t/acpi/ec.asl
new file mode 100644
index 0000000000..fe7115aa77
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/ec.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/z61t/acpi/gpe.asl b/src/mainboard/lenovo/z61t/acpi/gpe.asl
new file mode 100644
index 0000000000..3cc25b2d85
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/gpe.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "smi.h"
+Scope (\_GPE)
+{
+ Method(_L18, 0, NotSerialized)
+ {
+ /* Read EC register to clear wake status */
+ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+ /* So that we don't get a warning that Local0 is unused. */
+ Increment (Local0)
+ }
+}
diff --git a/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..f0d76db435
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
+ Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
+ Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
+ Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
+ Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
+ Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
+ Package() { 0x001dffff, 0, 0, 0x10 }, // USB
+ Package() { 0x001dffff, 1, 0, 0x11 }, // USB
+ Package() { 0x001dffff, 2, 0, 0x12 }, // USB
+ Package() { 0x001dffff, 3, 0, 0x13 }, // USB
+ Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
+ Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
+ Package() { 0x001fffff, 2, 0, 0x10 } // SATA
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
+ Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA
+ })
+ }
+}
diff --git a/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..4c7c3a3757
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+ })
+ } Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+ })
+}
diff --git a/src/mainboard/lenovo/z61t/acpi/mainboard.asl b/src/mainboard/lenovo/z61t/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/mainboard.asl
diff --git a/src/mainboard/lenovo/z61t/acpi/platform.asl b/src/mainboard/lenovo/z61t/acpi/platform.asl
new file mode 100644
index 0000000000..006b6f0ba2
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/platform.asl
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC.MUTE(1)
+ \_SB.PCI0.LPCB.EC.USBP(0)
+ \_SB.PCI0.LPCB.EC.RADI(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+ /* This method is placed on the top level, so we can make sure it's the
+ * first executed _INI method.
+ */
+ Method(_INI, 0)
+ {
+ /* The DTS data in NVS is probably not up to date.
+ * Update temperature values and make sure AP thermal
+ * interrupts can happen
+ */
+
+ // TRAP(71) // TODO
+
+ \GOS()
+
+ /* And the OS workarounds start right after we know what we're
+ * running: Windows XP SP1 needs to have C-State coordination
+ * enabled in SMM.
+ */
+ If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+ // TRAP(61) // TODO
+ }
+
+ /* SMM power state and C4-on-C3 settings need to be updated */
+ // TRAP(43) // TODO
+ }
+}
diff --git a/src/mainboard/lenovo/z61t/acpi/superio.asl b/src/mainboard/lenovo/z61t/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/superio.asl
diff --git a/src/mainboard/lenovo/z61t/acpi/video.asl b/src/mainboard/lenovo/z61t/acpi/video.asl
new file mode 100644
index 0000000000..6db3a44c9e
--- /dev/null
+++ b/src/mainboard/lenovo/z61t/acpi/video.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "smi.h"
+
+Scope (\)
+{
+ Method(BRTD, 0, NotSerialized)
+ {
+ Trap(SMI_BRIGHTNESS_DOWN)
+ \_SB.PCI0.GFX0.DECB()
+ }
+
+ Method(BRTU, 0, NotSerialized)
+ {
+ Trap(SMI_BRIGHTNESS_UP)
+ \_SB.PCI0.GFX0.INCB()
+ }
+}