diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-11-29 14:13:43 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-06 18:14:00 +0100 |
| commit | 62902ca45de871aa59657dd8ec1858c301595634 (patch) | |
| tree | 43b21ab2ec87ec5b41f875efb69be8bb494b0fa7 /src/mainboard/lenovo/x60/romstage.c | |
| parent | 40843efe5d6dddff19a0d7c8c5fe84c75448e739 (diff) | |
sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/lenovo/x60/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 43 |
1 files changed, 2 insertions, 41 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 53a0151fb9..51624a009e 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -35,48 +35,9 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> #include "dock.h" -void setup_ich7_gpios(void) -{ - printk(BIOS_DEBUG, " GPIOS..."); - - /* X60 GPIO: - * 1: HDD_PRESENCE# - * 6: Unknown (Pulled high by R215 to VCC3B) - * 7: BDC_PRESENCE# - * 8: H8_WAKE# - * 9: RTC_BAT_IN# - * 10: Unknown (Pulled high by R700 to VCC3M) - * 12: H8SCI# - * 13: SLICE_ON_3M# - * 14: Unknown (Pulled high by R321 to VCC3) - * 15: Unknown (Pulled high by R258 to VCC3) - * 19: Unknown (Pulled low by R594) - * 21: Unknown (Pulled high by R145 to VCC3) - * 22: FWH_WP# - * 25: MDC_KILL# - * 33: HDD_PRESENCE_2# - * 35: CLKREQ_SATA# - * 36: PLANARID0 - * 37: PLANARID1 - * 38: PLANARID2 - * 39: PLANARID3 - * 48: FWH_TBL# - */ - - outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfbf6ddfd, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100f2, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ -} - static void ich7_enable_lpc(void) { // Enable Serial IRQ @@ -222,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Enable GPIOs */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ - setup_ich7_gpios(); + setup_pch_gpios(&mainboard_gpio_map); ich7_enable_lpc(); |