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| author | Bill XIE <persmule@hardenedlinux.org> | 2020-05-18 16:34:37 +0800 |
|---|---|---|
| committer | Alexander Couzens <lynxis@fe80.eu> | 2020-05-21 02:50:08 +0000 |
| commit | cfd78b1500bed6d3d410f984450c45f28b700aa2 (patch) | |
| tree | 4a3380312f079f6b5639c0b47411268b4bbf1e06 /src/mainboard/lenovo/x230/devicetree.cb | |
| parent | 238b10a5f7fb3ca6c4aca37a14f34cafa4306ddf (diff) | |
Revert "mainboard/lenovo/x230: Add ThinkPad x230s as a variant"
This reverts commit 6b95507ec5b087658178a325bdc68570bc48bb20, in order
to recommit and review it again.
Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/x230/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/x230/devicetree.cb | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 52a4cd3e47..e34734c4c3 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -60,8 +60,7 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - # Wire port 4 (wwan usb) to ehci for it lacks superspeed components - register "xhci_switchable_ports" = "0x7" + register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" @@ -90,7 +89,9 @@ chip northbridge/intel/sandybridge end end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 + device pci 1c.2 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -135,6 +136,7 @@ chip northbridge/intel/sandybridge register "event7_enable" = "0x01" register "event8_enable" = "0x7b" register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" register "eventb_enable" = "0x00" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" |