diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-13 22:30:12 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-14 23:27:35 +0000 |
| commit | c1a0e128a08a119bd5eda868594428cb02837d2a (patch) | |
| tree | 2332e22c8c86f2b283f71a848bd2594a51ab5f55 /src/mainboard/lenovo/x220/variants | |
| parent | 7fc6114f8921f5bf9bc07fdac9653c97be7421a1 (diff) | |
mb/lenovo/x220: Remove superfluous comments related to PCI devices
Since all devicetrees from lenovo/x220 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/mainboard/lenovo/x220/variants')
| -rw-r--r-- | src/mainboard/lenovo/x220/variants/x1/overridetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x220/variants/x220/overridetree.cb | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index 2defac8c1c..bf88150044 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -21,10 +21,10 @@ chip northbridge/intel/sandybridge # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp3 off end # PCIe Port #3 - device ref pcie_rp4 off end # PCIe Port #4 - device ref lpc on #LPC bridge + device ref pcie_rp1 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config2" = "0xe0" @@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" end - end # LPC bridge + end end end end diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 932548095c..b9caa255de 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,13 +1,13 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device ref lpc on #LPC bridge + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "eventa_enable" = "0x01" register "eventb_enable" = "0xf0" end - end # LPC bridge + end end end end |