summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/x201/devicetree.cb
diff options
context:
space:
mode:
authorPatrick Rudolph <siro@das-labor.org>2016-06-09 18:13:34 +0200
committerMartin Roth <martinroth@google.com>2016-06-12 12:48:44 +0200
commit266a1f794dc28053e97794cbeb3f1a588137698b (patch)
tree7cb11796fa351bd50d15af6be9508a15be223192 /src/mainboard/lenovo/x201/devicetree.cb
parente7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff)
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/x201/devicetree.cb')
-rw-r--r--src/mainboard/lenovo/x201/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 23745540f8..bd6490e889 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -80,6 +80,8 @@ chip northbridge/intel/nehalem
end
end
+ register "pci_mmio_size" = "1024"
+
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2193