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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-07-13 01:21:16 +0200 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-07-14 03:06:07 +0000 |
| commit | afcd48a2f16592f972f635783048024b2a06a771 (patch) | |
| tree | dc0febf884a6e75ffc460855d8fbb356eafffe42 /src/mainboard/lenovo/x200/board_info.txt | |
| parent | 2f7c7e8a77e1e6e46366a294f3ab2cf2c0755652 (diff) | |
vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode comment
When set to 1, the link_compliance_mode element of the DXIO port
descriptor will cause the corresponding PCIe port to not be trained but
to output a compliance testing pattern instead. Update the comment to
point out that this is only a testing mode.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/lenovo/x200/board_info.txt')
0 files changed, 0 insertions, 0 deletions