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authorArthur Heymans <arthur@aheymans.xyz>2022-11-12 14:51:49 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2023-02-04 01:42:39 +0000
commitb5df65a9aaee50421913ace6d7a4b35e0ddff676 (patch)
treeaa885e29c4e724f4fb583bca5c93fe1243e95da2 /src/mainboard/lenovo/t520
parent9ce7935b490830a709c62e271bf269801520ec29 (diff)
mb/*: Replace SNB PCI devices with references from chipset.cb
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/lenovo/t520')
-rw-r--r--src/mainboard/lenovo/t520/devicetree.cb45
1 files changed, 22 insertions, 23 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 55c8d981fd..7ef12ba2ac 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -18,9 +18,9 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x17aa 0x21cf inherit
- device pci 00.0 on end # host bridge
- device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
- device pci 02.0 on
+ device ref host_bridge on end # host bridge
+ device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M]
+ device ref igd on
subsystemid 0x17aa 0x21d1
end # vga controller
@@ -50,28 +50,27 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end
- device pci 16.2 off end
- device pci 16.3 off end
- device pci 19.0 on # Intel Gigabit Ethernet
+ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on # Intel Gigabit Ethernet
subsystemid 0x17aa 0x21ce
end
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 off end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 on
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 off end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN
+ device ref pcie_rp3 off end # PCIe Port #3
+ device ref pcie_rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4 Express Card
- device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394
- device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI-2-PCI bridge
- device pci 1f.0 on #LPC bridge
+ device ref pcie_rp5 on end # PCIe Port #5 MMC/SDXC + IEEE1394
+ device ref pcie_rp6 off end # PCIe Port #6 Intel Ethernet PHY
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref lpc on #LPC bridge
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
register "backlight_enable" = "0x01"
@@ -131,8 +130,8 @@ chip northbridge/intel/sandybridge
register "has_thinker1" = "1"
end
end # LPC bridge
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on # SMBUS controller
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on # SMBUS controller
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end