diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-13 22:36:06 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-14 23:31:38 +0000 |
| commit | e47c3487056c7ac5d5e967c728f9fb36aaab1b63 (patch) | |
| tree | 65720191d2b27c0acea0844934974c7c059ab21f /src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | |
| parent | 7563a32981cb4708c1b268cbbb6c0dbe746f666d (diff) | |
mb/lenovo/t430: Convert remaining PCI numbers into reference names
Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index fcd137f9f7..3e13627d61 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x17aa 0x2208 inherit - device pci 01.0 off end # PCIe Bridge for discrete graphics + device ref peg10 off end # PCIe Bridge for discrete graphics chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) @@ -23,15 +23,15 @@ chip northbridge/intel/sandybridge # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "0" device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.2 off end # PCIe Port #3 - device pci 1f.0 on + device ref pcie_rp3 off end # PCIe Port #3 + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config0" = "0xa6" @@ -42,7 +42,7 @@ chip northbridge/intel/sandybridge register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.6 off end # Thermal + device ref thermal off end # Thermal end end end |