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| author | Anastasios Koutian <akoutian2@gmail.com> | 2024-05-07 20:46:59 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-07-15 16:35:24 +0000 |
| commit | 524fc52bdd0d28021484b71f321e7a511fe37cc6 (patch) | |
| tree | 297b09bd38b7ea1e9de8e3706b20e5de1579879f /src/mainboard/lenovo/t420 | |
| parent | 3c9944ea4127c69cc262a44830d941ee1861f0f8 (diff) | |
mb/lenovo/t420: Use vendor default power limits
Also set the vendor default TCC offset temperature
Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/t420')
| -rw-r--r-- | src/mainboard/lenovo/t420/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 6b721f3f74..65891f0c30 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -18,6 +18,11 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x51, 0}" chip cpu/intel/model_206ax # Values obtained from vendor BIOS + register "tcc_offset" = "3" + register "pl1_mw" = "35000" + register "pl2_mw" = "43750" + register "pp0_current_limit" = "97" + register "pp1_current_limit" = "32" register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" |