diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-09 13:09:07 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:44:44 +0000 |
| commit | 9b7ae2f3fccd9fd568dbc33b91bec8a0162754ee (patch) | |
| tree | f2eae796ded12c7802bfb85be3bb4e1edafbdb8b /src/mainboard/lenovo/s230u | |
| parent | 84fbc30e928d28fba2f3a25f6ccea3a831dce648 (diff) | |
mb/lenovo/*/romstage: Use macros instead of magic numbers
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead. Also removed FDD from l520
romstage (original value, 0x3c0c, means that FDD_LPC_EN was also
enabled).
Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/s230u')
| -rw-r--r-- | src/mainboard/lenovo/s230u/romstage.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 7e002d4715..f4241dbba5 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -32,18 +32,17 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); + pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Memory map KB9012 EC registers */ pci_write_config32( - PCI_DEV(0, 0x1f, 0), 0x98, + PCH_LPC_DEV, LGMR, CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); /* Enable external USB port power. */ if (IS_ENABLED(CONFIG_USBDEBUG)) @@ -53,7 +52,7 @@ void pch_enable_lpc(void) void mainboard_rcba_config(void) { /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; + RCBA32(BUC) = 0x00000020; } const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, |