mb/lenovo: Add ThinkCentre M920q (Coffee Lake)

It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here.

Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
- PCIe x8 port (x8 riser tested, x4 not)

Does not work:
- front audio jacks

Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 719 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/m920q/Kconfig b/src/mainboard/lenovo/m920q/Kconfig
new file mode 100644
index 0000000000..a83b477a54
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/Kconfig
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_LENOVO_M920Q
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_24576
+	select DRIVERS_UART_8250IO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SUPERIO_NUVOTON_NCT6687D
+
+config MAINBOARD_DIR
+	default "lenovo/m920q"
+
+config MAINBOARD_PART_NUMBER
+	default "ThinkCentre M920 Tiny"
+
+config CBFS_SIZE
+	default 0x900000
+
+endif
diff --git a/src/mainboard/lenovo/m920q/Kconfig.name b/src/mainboard/lenovo/m920q/Kconfig.name
new file mode 100644
index 0000000000..ccdd21a237
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/Kconfig.name
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_M920Q
+	bool "ThinkCentre M920 Tiny"
diff --git a/src/mainboard/lenovo/m920q/Makefile.mk b/src/mainboard/lenovo/m920q/Makefile.mk
new file mode 100644
index 0000000000..4be83458d1
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/Makefile.mk
@@ -0,0 +1,12 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/m920q/acpi/ec.asl b/src/mainboard/lenovo/m920q/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/m920q/acpi/mainboard.asl b/src/mainboard/lenovo/m920q/acpi/mainboard.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/acpi/mainboard.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/m920q/acpi/superio.asl b/src/mainboard/lenovo/m920q/acpi/superio.asl
new file mode 100644
index 0000000000..13623c5cbb
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/acpi/superio.asl
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define NCT6687D_SHOW_SP1
+#define NCT6687D_SHOW_EC
+
+#include <superio/nuvoton/nct6687d/acpi/superio.asl>
diff --git a/src/mainboard/lenovo/m920q/board_info.txt b/src/mainboard/lenovo/m920q/board_info.txt
new file mode 100644
index 0000000000..02e3e322eb
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://psref.lenovo.com/Product/ThinkCentre_M920_Tiny
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2021
diff --git a/src/mainboard/lenovo/m920q/bootblock.c b/src/mainboard/lenovo/m920q/bootblock.c
new file mode 100644
index 0000000000..7839cf7fb8
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/bootblock.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP2)
+#define POWER_DEV  PNP_DEV(0x2e, NCT6687D_SLEEP_PWR)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Replicate vendor settings for multi-function pins in global config LDN */
+	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+	pnp_write_config(SERIAL_DEV, 0x13, 0xff);
+	pnp_write_config(SERIAL_DEV, 0x14, 0xff);
+
+	/* Below are multi-pin function */
+	pnp_write_config(SERIAL_DEV, 0x1b, 0xf8);
+	pnp_write_config(SERIAL_DEV, 0x1f, 0xf0);
+	pnp_write_config(SERIAL_DEV, 0x20, 0xd4);
+	pnp_write_config(SERIAL_DEV, 0x21, 0x41);
+	pnp_write_config(SERIAL_DEV, 0x22, 0xbc);
+	pnp_write_config(SERIAL_DEV, 0x23, 0xff);
+	pnp_write_config(SERIAL_DEV, 0x24, 0x07);
+	pnp_write_config(SERIAL_DEV, 0x25, 0xff);
+	pnp_write_config(SERIAL_DEV, 0x26, 0x80);
+	pnp_write_config(SERIAL_DEV, 0x28, 0x08);
+	pnp_write_config(SERIAL_DEV, 0x29, 0x95);
+	pnp_write_config(SERIAL_DEV, 0x2a, 0xcf);
+
+	pnp_set_logical_device(POWER_DEV);
+	/* Configure pin for PECI */
+	pnp_write_config(POWER_DEV, 0xf3, 0x18);
+
+	nuvoton_pnp_exit_conf_state(POWER_DEV);
+
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lenovo/m920q/cmos.default b/src/mainboard/lenovo/m920q/cmos.default
new file mode 100644
index 0000000000..f3330e5070
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
diff --git a/src/mainboard/lenovo/m920q/cmos.layout b/src/mainboard/lenovo/m920q/cmos.layout
new file mode 100644
index 0000000000..4dea5d2469
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/cmos.layout
@@ -0,0 +1,59 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID	name
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: cpu
+400	1	e	2	hyper_threading
+
+# coreboot config options: southbridge
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416	128	r	0	vbnv
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Disable
+2	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/lenovo/m920q/data.vbt b/src/mainboard/lenovo/m920q/data.vbt
new file mode 100644
index 0000000000..38acf19c20
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/data.vbt
diff --git a/src/mainboard/lenovo/m920q/devicetree.cb b/src/mainboard/lenovo/m920q/devicetree.cb
new file mode 100644
index 0000000000..61fa868a76
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/devicetree.cb
@@ -0,0 +1,142 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/cannonlake
+	register "power_limits_config" = "{
+		.tdp_pl2_override = 65,
+	}"
+
+	# Unmap unused CLKREQ lines, otherwise CLKSRC #0 won't work
+	register "PcieClkSrcClkReq[1]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[7]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[8]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[9]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[11]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[12]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[13]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[14]"	= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[15]"	= "PCIE_CLK_NOTUSED"
+
+	device domain 0 on
+		subsystemid 0x17aa 0x3136 inherit
+		# Slot JP3
+		device ref peg0 		on
+			register "PcieClkSrcUsage[0]"	= "0x40"
+			register "PcieClkSrcClkReq[0]"	= "0"
+		end
+		device ref igpu 		on	end
+		device ref dptf 		on	end
+		device ref thermal 		on	end
+		device ref xhci 		on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),		// Internal USB header
+				[1] = USB2_PORT_TYPE_C(OC1),		// Front port (charger)
+				[3] = USB2_PORT_TYPE_C(OC2),		// Front Type C port
+				[4] = USB2_PORT_MID(OC4),		// Rear USB 3.1 port 1
+				[5] = USB2_PORT_MID(OC6),		// Rear USB 3.1 port 2
+				[6] = USB2_PORT_MID(OC3),		// Rear USB 3.0 port 1
+				[7] = USB2_PORT_MID(OC5),		// Rear USB 3.0 port 2
+				[13] = USB2_PORT_SHORT(OC_SKIP),	// M.2 2230
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),	// Front port (charger)
+				[1] = USB3_PORT_DEFAULT(OC2),	// Front Type C port
+				[2] = USB3_PORT_DEFAULT(OC4),	// Rear USB 3.1 port 1
+				[3] = USB3_PORT_DEFAULT(OC6),	// Rear USB 3.2 port 2
+				[4] = USB3_PORT_DEFAULT(OC3),	// Rear USB 3.0 port 1
+				[5] = USB3_PORT_DEFAULT(OC5),	// Rear USB 3.0 port 2
+				[6] = USB3_PORT_DEFAULT(OC0),	// Internal USB header
+			}"
+		end
+		device ref shared_sram	on	end
+		device ref cnvi_wifi	on
+			chip drivers/wifi/generic
+				register "wake" = "PME_B0_EN_BIT"
+				device generic 0 on end
+			end
+		end
+		device ref heci1	on	end
+		device ref heci3	on	end
+		device ref sata		on
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable" = "{
+				[0] = 1, // on-board SATA1
+				[4] = 1, // M.2 SATA on M920x
+			}"
+		end
+
+		device ref pcie_rp6	on # WLAN
+			register "PcieRpEnable[5]"		= "1"
+			register "PcieRpSlotImplemented[5]"	= "1"
+			register "PcieClkSrcUsage[3]"		= "5"
+			register "PcieClkSrcClkReq[3]"		= "3"
+		end
+
+		device ref pcie_rp9	on # PCIe x4
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieClkSrcUsage[2]"		= "8"
+			register "PcieClkSrcClkReq[2]"		= "2"
+		end
+
+		device ref pcie_rp17 on # M.2 SSD #2
+			register "PcieRpEnable[16]"		= "1"
+			register "PcieRpSlotImplemented[16]"	= "1"
+			register "PcieClkSrcUsage[10]"		= "16"
+			register "PcieClkSrcClkReq[10]"		= "10"
+		end
+
+		device ref pcie_rp21 on # M.2 SSD #1
+			register "PcieRpEnable[20]"		= "1"
+			register "PcieRpSlotImplemented[20]"	= "1"
+			register "PcieClkSrcUsage[4]"		= "20"
+			register "PcieClkSrcClkReq[4]"		= "4"
+		end
+
+		device ref lpc_espi	on
+			chip superio/nuvoton/nct6687d
+				device pnp 2e.1 off	end	# Parallel port
+				device pnp 2e.2 off	end	# UARTA (USB debug port?)
+				device pnp 2e.3 on		# UARTB - COM1 header - optional sub-board
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+					irq 0xf0 = 0
+					irq 0xf1 = 0
+				end
+				device pnp 2e.5 off	end	# Keyboard
+				device pnp 2e.6 off	end	# CIR
+				device pnp 2e.7 off	end	# GPIO0-7
+				device pnp 2e.8 off	end	# P80 UART
+				device pnp 2e.9 off	end	# GPIO8-9, GPIO1-8 AF
+				device pnp 2e.a on		# ACPI
+					io 0x60 = 0x00
+					irq 0x70 = 0x40
+				end
+				device pnp 2e.b on		# EC
+					io 0x60 = 0xa20
+					irq 0x70 = 0
+				end
+				device pnp 2e.c off	end	# RTC
+				device pnp 2e.d off	end	# Deep Sleep
+				device pnp 2e.e on		# TACH/PWM assignment
+					irq 0xe4 = 0x10
+					irq 0xe5 = 0x09
+				end
+				device pnp 2e.f off	end	# Function register
+			end
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on	end
+			end
+		end
+		device ref hda	on
+			register "PchHdaAudioLinkHda"	= "1"
+		end
+		device ref smbus	on	end
+		device ref fast_spi	on	end
+		device ref gbe	on
+			register "PcieClkSrcUsage[6]"	= "PCIE_CLK_LAN"
+			register "PcieClkSrcClkReq[6]"	= "6"
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/m920q/dsdt.asl b/src/mainboard/lenovo/m920q/dsdt.asl
new file mode 100644
index 0000000000..09825c3b5c
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/m920q/gma-mainboard.ads b/src/mainboard/lenovo/m920q/gma-mainboard.ads
new file mode 100644
index 0000000000..fa35825af4
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/m920q/gpio.c b/src/mainboard/lenovo/m920q/gpio.c
new file mode 100644
index 0000000000..339d819199
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/gpio.c
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_NC(GPP_A0, NONE),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3),	/* ESPI_IO0 */
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3),	/* ESPI_IO1 */
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3),	/* ESPI_IO2 */
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3),	/* ESPI_IO3 */
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF3),	/* ESPI_CS0# */
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3),	/* ESPI_CLK */
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3),	/* ESPI_RESET# */
+	PAD_NC(GPP_A15, NONE),
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_NC(GPP_B0, NONE),
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),	/* SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),	/* SRCCLKREQ1# */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),	/* SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),	/* SRCCLKREQ3# */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),	/* SRCCLKREQ4# */
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1),	/* SLP_S0# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),	/* PLTRST# */
+	PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),	/* SPKR */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, PLTRST, OFF, ACPI),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),	/* SMBCLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),	/* SMBDATA */
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),	/* SML0CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),	/* SML0DATA */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST, LEVEL, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_CFG_GPO(GPP_D1, 1, PLTRST),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),	/* CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),	/* MODEM_CLKREQ */
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),	/* GP_BSSB_DI */
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),	/* DMIC_CLK1 */
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),	/* DMIC_DATA1 */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),	/* DMIC_CLK0 */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),	/* DMIC_DATA0 */
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),	/* BATLOW# */
+	PAD_CFG_GPI_TRIG_OWN(GPD1, UP_20K, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1),	/* PRWBTN# */
+	PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),	/* SLP_S3# */
+	PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),	/* SLP_S4# */
+	PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),	/* SLP_A# */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),
+	PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),	/* SUSCLK */
+	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),	/* SLP_WLAN# */
+	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),	/* SLP_S5# */
+	PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),	/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_NC(GPP_K0, NONE),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_NC(GPP_K3, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K9, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_K10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF(GPP_K11, NONE, DEEP, NF1),	/* Reserved */
+	PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, LEVEL, INVERT),
+	PAD_NC(GPP_K13, NONE),
+	PAD_NC(GPP_K14, NONE),
+	PAD_NC(GPP_K15, NONE),
+	PAD_CFG_GPO(GPP_K16, 0, PLTRST),
+	PAD_NC(GPP_K17, NONE),
+	PAD_NC(GPP_K18, NONE),
+	PAD_NC(GPP_K19, NONE),
+	PAD_CFG_NF(GPP_K20, NONE, DEEP, NF1),	/* Reserved */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_K22, 1, PLTRST),
+	PAD_NC(GPP_K23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),	/* SRCCLKREQ6# */
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),	/* SRCCLKREQ10# */
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_NC(GPP_H13, NONE),
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+	PAD_NC(GPP_H15, NONE),
+	PAD_CFG_GPO(GPP_H16, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H17, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),	/* SATAXPCIE0 */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),	/* SATAXPCIE1 */
+	PAD_CFG_GPI_SCI(GPP_E2, NONE, PLTRST, LEVEL, NONE),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, PLTRST),
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),	/* SATALED# */
+	PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),	/* USB2_OC0# */
+	PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),	/* USB2_OC1# */
+	PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),	/* USB2_OC2# */
+	PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),	/* USB2_OC3# */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),	/* SATAXPCIE3 */
+	PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1),	/* SATAXPCIE4 */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),	/* SATAXPCIE5 */
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),	/* SATAXPCIE6 */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),	/* SATAXPCIE7 */
+	PAD_NC(GPP_F5, NONE),
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),	/* PS_ON# */
+	PAD_CFG_NF(GPP_F15, NONE, PLTRST, NF1),	/* USB2_OC4# */
+	PAD_CFG_NF(GPP_F16, NONE, PLTRST, NF1),	/* USB2_OC5# */
+	PAD_CFG_NF(GPP_F17, NONE, PLTRST, NF1),	/* USB2_OC6# */
+	PAD_NC(GPP_F18, NONE),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),	/* eDP_VDDEN */
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),	/* eDP_BKLTEN */
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),	/* eDP_BKLTCTL */
+	PAD_CFG_GPO(GPP_F22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F23, 1, PLTRST),
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),	/* DDPB_HPD0 */
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),	/* DDPB_HPD1 */
+	PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),	/* DDPB_HPD2 */
+	PAD_NC(GPP_I3, NONE),
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),	/* EDP_HPD */
+	PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),	/* DDPB_CTRLCLK */
+	PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),	/* DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),	/* DDPC_CTRLCLK */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),	/* DDPC_CTRLDATA */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),	/* DDPD_CTRLCLK */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),	/* DDPD_CTRLDATA */
+	PAD_NC(GPP_I11, NONE),
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_NC(GPP_J0, NONE),
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),	/* CPU_C10_GATE# */
+	PAD_NC(GPP_J2, NONE),
+	PAD_NC(GPP_J3, NONE),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),	/* CNV_BRI_DT */
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),	/* CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),	/* CNV_RGI_DT */
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),	/* CNV_RGI_RSP */
+	PAD_NC(GPP_J8, NONE),
+	PAD_CFG_GPO(GPP_J9, 0, DEEP),
+	PAD_NC(GPP_J10, NONE),
+	PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),	/* A4WP_PRESENT */
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/m920q/hda_verb.c b/src/mainboard/lenovo/m920q/hda_verb.c
new file mode 100644
index 0000000000..6e6d679e26
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0235,	/* Codec Vendor / Device ID: Realtek ALC233 */
+	0x17aa3136,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x17aa3136),
+	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a11020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, 0x0221101f),
+
+	0x8086280b,	/* Codec Vendor / Device ID: Intel Kabylake HDMI */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/m920q/include/mainboard/gpio.h b/src/mainboard/lenovo/m920q/include/mainboard/gpio.h
new file mode 100644
index 0000000000..ef2a21c418
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/include/mainboard/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/lenovo/m920q/ramstage.c b/src/mainboard/lenovo/m920q/ramstage.c
new file mode 100644
index 0000000000..e94ca02030
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/ramstage.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/m920q/romstage.c b/src/mainboard/lenovo/m920q/romstage.c
new file mode 100644
index 0000000000..99f0f68119
--- /dev/null
+++ b/src/mainboard/lenovo/m920q/romstage.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg baseboard_mem_cfg = {
+	/* Access memory info through SMBUS. */
+	.spd[0] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa0}},
+	.spd[1] = {.read_type = READ_SMBUS, .spd_spec = {.spd_smbus_address = 0xa4}},
+
+	/* Rcomp resistors on CFL-S are located on the CPU itself */
+	.rcomp_resistor = {121, 75, 100},
+
+	/* Rcomp target values for CFL-S, DDR4 and 1 DIMM per channel */
+	.rcomp_targets = {50, 26, 20, 20, 26},
+
+	/* Baseboard is an interleaved design */
+	.dq_pins_interleaved = 1,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Disable Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &baseboard_mem_cfg);
+}