diff options
author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-23 17:38:52 +1100 |
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committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 11:28:24 +0100 |
commit | 32960e30f08f678355b20b5702e8028351a7275e (patch) | |
tree | 8a44ac8674c02286bccb63bf8286645b3c3c367b /src/mainboard/lenovo/g505s/acpi/gpe.asl | |
parent | b06eaf76b5142977aa130c22f09a97ad08bef036 (diff) |
mainboard/lenovo/g505s: New port Richland APU A10-5750M
Richland APU A10-5750M
8GB RAM
4MB Flash
Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.
Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/g505s/acpi/gpe.asl')
-rw-r--r-- | src/mainboard/lenovo/g505s/acpi/gpe.asl | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl new file mode 100644 index 0000000000..3bf072131a --- /dev/null +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + Store("USB PME", Debug) + /* Notify devices of wake event */ + Notify(\_SB.PCI0.UOH1, 0x02) + Notify(\_SB.PCI0.UOH2, 0x02) + Notify(\_SB.PCI0.UOH3, 0x02) + Notify(\_SB.PCI0.UOH4, 0x02) + Notify(\_SB.PCI0.XHC0, 0x02) + Notify(\_SB.PCI0.UEH1, 0x02) + Notify(\_SB.PWRB, 0x02) + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* Lid switch opened or closed */ + Method(_L16) { + Store("Lid status changed", Debug) + /* Flip trigger polarity */ + Not(LPOL, LPOL) + /* Notify lid object of status change */ + Notify(\_SB.LID, 0x80) + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + Store("PCI bridge wake event", Debug) + /* Notify PCI bridges of wake event */ + Notify(\_SB.PCI0.PBR4, 0x02) + Notify(\_SB.PCI0.PBR5, 0x02) + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ |