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authorArthur Heymans <arthur@aheymans.xyz>2021-01-28 12:20:42 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 12:34:52 +0000
commit93cb1809a2034aa398ad0cb5faf7d5e8e48bfe44 (patch)
tree036465f6867dda03a8a164d802beda00f0d95ee0 /src/mainboard/kontron
parentdd5fe14759635b1bb4cacde77df79233d65dbadc (diff)
cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE
This fixes a regression introduced by Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE) where the CAR base is not aligned to its size. Change-Id: If54cb178e86426e1491dda4047302632d876a8f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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