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author | Shuo Liu <shuo.liu@intel.com> | 2024-03-07 07:38:36 +0800 |
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committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-12 11:32:00 +0000 |
commit | a454b6293743f12c8387a7b6a15f0b29715e39d6 (patch) | |
tree | 18e1d745276c8dfbb59db260cd63846fc4e8f01b /src/mainboard/kontron/bsl6 | |
parent | c4e68f6080a3ca0f678efce14d778b5602120865 (diff) |
soc/intel/xeon_sp: Create CXL domains
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain
is a PCI domain with single bus number and PCIe RCiEPs (Root
Complex Integrated End Points) on it. The 2nd domain is a CXL
domain with remaining buses for CXL 1.0/1.1 end points and
possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual
Function) if any.
TEST=intel/archercity CRB
P.S. The SUT is not with CXL cards however we hope this refactor
could be integrated first as an improvement of the design.
Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/kontron/bsl6')
0 files changed, 0 insertions, 0 deletions