diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-07-08 04:29:39 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-12 20:08:01 +0000 |
| commit | 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch) | |
| tree | 9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/kontron/bsl6/variants | |
| parent | 702902d71fae63fd35362c82f2a369b42af1a77f (diff) | |
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/kontron/bsl6/variants')
| -rw-r--r-- | src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index b6b3574921..9cf710f2eb 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake - # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) - register "PcieRpEnable[ 0]" = "1" - register "PcieRpEnable[ 1]" = "1" - register "PcieRpEnable[ 2]" = "1" - register "PcieRpEnable[ 3]" = "1" - register "PcieRpEnable[11]" = "1" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -27,11 +20,26 @@ chip soc/intel/skylake device ref sata on register "SataPortsEnable[3]" = "1" end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp12 on end + device ref pcie_rp1 on + # COMe 4 + register "PcieRpEnable[0]" = "1" + end + device ref pcie_rp2 on + # COMe 5 + register "PcieRpEnable[1]" = "1" + end + device ref pcie_rp3 on + # COMe 6 + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + # COMe 7 + register "PcieRpEnable[3]" = "1" + end + device ref pcie_rp12 on + # COMe 3 + register "PcieRpEnable[11]" = "1" + end device ref smbus on chip drivers/i2c/nct7802y register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" |