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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-22 16:46:31 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-28 18:36:35 +0200
commit2458f42b27e6525f4131899ef36f21d0f7dace1a (patch)
treeb3f5ece33c604ddc9638da1f192b3e8361216d65 /src/mainboard/jetway
parentcf7b4989083cb3fd1adf34dc5e07d4ac253e8f85 (diff)
AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/romstage.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 3e962d3274..848faf725f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -38,6 +38,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/amd/car.h>
#include <sb_cimx.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <superio/fintek/common/fintek.h>
@@ -47,9 +48,6 @@
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)