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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-04-19 07:17:59 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-05-18 10:44:43 +0200
commit08311f5033e3adccb8794b6113d72bf7a76e4d00 (patch)
treeaaf0d1ca6cacf2d5a73e45dc9f9193417a4b10fc /src/mainboard/jetway/nf81-t56n-lf
parent82171ea0ff9e38462e813b791dd57c8ad95dc768 (diff)
AGESA vendorcode: Build a common amdlib
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 038ad8b0ec..37caa6ef45 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -16,7 +16,7 @@
#include "AGESA.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <Lib/amdlib.h>
+#include <amdlib.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index d0a989277e..a91bd0f2c2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -18,7 +18,7 @@
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f14/AGESA.h>
-#include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
+#include <amdlib.h>
/**
* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)