Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.

Step 2: change the Persimmon code to adapt it to the new board's hardware.

The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
  - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
  - VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
  - 6x USB 2.0/1.1 ports
  - 5x SATA3 6Gb/s, 1x mSATA socket
  - 6-Channel HD Audio (via VIA VT1705)
  - PCI and ISA (via ITE IT8888)??
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
  - PS/2 KB/MS port
  - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
  - GPIO header
  - CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)

Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.

Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4801
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 45 insertions, 21 deletions

diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 8b1acd5bb3..347d4a6d47 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
 						device pci 0.0 on end # Root Complex
 						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-						device pci 4.0 on end # PCIE P2P bridge on-board NIC
+#						device pci 1.1 on end # Internal Audio P2P bridge 0x1314
+						device pci 4.0 off end
 						device pci 5.0 off end # PCIE P2P bridge
 						device pci 6.0 on end # PCIE P2P bridge PCIe slot
 						device pci 7.0 off end # PCIE P2P bridge
@@ -50,47 +52,64 @@ chip northbridge/amd/agesa/family14/root_complex
 							device i2c 51 on end
 						end
 					end # SM
-					device pci 14.1 on end # IDE	0x439c
+					device pci 14.1 off end # IDE	0x439c
 					device pci 14.2 on end # HDA	0x4383
 					device pci 14.3 on # LPC		0x439d
-					chip superio/fintek/f81865f
-						device pnp 4e.0 off		# Floppy
+					chip superio/fintek/f71869ad
+# XXX: 4e is the default index port and .xy is the
+# LDN indexing the pnp_info array found in the superio.c
+# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
+#     see page 18 from Fintek F71869 V1.1 datasheet.
+						device pnp 2e.00 off		# Floppy
 							io 0x60 = 0x3f0
 							irq 0x70 = 6
 							drq 0x74 = 2
 						end
-						device pnp 4e.3 off end			# Parallel Port
-						device pnp 4e.4 off end			# Hardware Monitor
-						device pnp 4e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 4e.6 off end			# GPIO
-						device pnp 4e.a off end			# PME
-						device pnp 4e.10 on			# COM1
+						device pnp 2e.01 on			# COM1
 							io 0x60 = 0x3f8
 							irq 0x70 = 4
 						end
-						device pnp 4e.11 on			# COM2
+# COM2 not physically wired on board.
+						device pnp 2e.02 off		# COM2
 							io 0x60 = 0x2f8
 							irq 0x70 = 3
 						end
-					end # f81865f
+						device pnp 2e.03 off		# Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+							drq 0x74 = 3
+						end
+						device pnp 2e.04 on			# Hardware Monitor
+							io 0x60 = 0x295
+							irq 0x70 = 0
+						end
+						device pnp 2e.05 on # KBC
+							io 0x60 = 0x060
+							irq 0x70 = 1 # Keyboard IRQ
+							irq 0x72 = 12 # Mouse IRQ
+						end
+						device pnp 2e.06 off end	# GPIO
+# TODO: Verify BSEL register content with vendor BIOS using
+# $ sudo isadump 0x4e 0x4f 0x7
+# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
+						device pnp 2e.07 on end		# BSEL
+						device pnp 2e.0a off end	# PME
+					end # f71869ad
 				end #LPC
 				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-				device pci 14.5 off end # OHCI FS/LS USB
+				device pci 14.5 on end # OHCI FS/LS USB (0x4399)
 				device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-				device pci 15.0 off end # PCIe PortA
+				device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
 				device pci 15.1 off end # PCIe PortB
 				device pci 15.2 off end # PCIe PortC
 				device pci 15.3 off end # PCIe PortD
-				device pci 16.0 off end # OHCI USB 10-13
-				device pci 16.2 off end # EHCI USB 10-13
+				device pci 16.0 on end # OHCI USB 10-13 (0x4397)
+				device pci 16.2 on end # EHCI USB 10-13 (0x4396)
 				register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 
-				#set up SB800 Fan control registers and IMC fan controls
+				# Set up SB800 Fan control registers and IMC fan controls
+                # TODO: verify SB handles the HW monitor and not the super io (PME)
 				register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
 				register "fan0_enabled" = "1"
 				register "fan1_enabled" = "1"
@@ -150,6 +169,11 @@ chip northbridge/amd/agesa/family14/root_complex
 			device pci 18.6 on end
 			device pci 18.7 on end
 
+#
+# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
+# with i2cdump tool.
+# Notes:  0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+#
 			register "spdAddrLookup" = "
 			{
 				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses