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authorStefan Reinauer <stepan@coresystems.de>2010-04-09 20:36:29 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-09 20:36:29 +0000
commit314e551447f408300e56cd6206af3e52d9b22059 (patch)
tree47fe0ed174ae5e2e7c5fe2bafdbb5e050acb17e8 /src/mainboard/jetway/j7f24
parentfbb02a5f9d8aa04ce69ed955f739022a1e0dce9f (diff)
This patch changes C7 CAR code to be a single assembler file instead
of the ugly mixture it was before. It also enables CAR for all C7 boards Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway/j7f24')
-rw-r--r--src/mainboard/jetway/j7f24/Kconfig10
-rw-r--r--src/mainboard/jetway/j7f24/romstage.c2
2 files changed, 1 insertions, 11 deletions
diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig
index 6890f1a45e..e1afc27e8a 100644
--- a/src/mainboard/jetway/j7f24/Kconfig
+++ b/src/mainboard/jetway/j7f24/Kconfig
@@ -14,16 +14,6 @@ config MAINBOARD_DIR
default jetway/j7f24
depends on BOARD_JETWAY_J7F24
-#config DCACHE_RAM_BASE
-# hex
-# default 0xffef0000
-# depends on BOARD_JETWAY_J7F24
-#
-#config DCACHE_RAM_SIZE
-# hex
-# default 0x8000
-# depends on BOARD_JETWAY_J7F24
-
config MAINBOARD_PART_NUMBER
string
default "J7f24"
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 67eda8e8b5..3903684945 100644
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -87,7 +87,7 @@ static const struct mem_controller ctrl = {
.channel0 = { 0x50 },
};
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);